74LVC00APW-Q100J

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Nexperia USA Inc.

NAND GATE, QUAD, 2 INPUT, 14 PINS, TSSOP, 74LVC00A

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74LVC00APW-Q100J

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Nexperia USA Inc.

NAND GATE, QUAD, 2 INPUT, 14 PINS, TSSOP, 74LVC00A

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Description Specifications Series Pricing CAD Documents

Description

General part information

74LVC00APW-Q100 Series

The 74LVC00A-Q100 is a quad 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Technical Specifications

Parameters and characteristics for this part

Specification	74LVC00APW-Q100J

Current - Output High	24 mA
Current - Output Low	24 mA
Current - Quiescent (Max)	40 ĄA
Grade	Automotive
Input Logic Level - High (Max)	2 V
Input Logic Level - High (Min)	1.08 V
Input Logic Level - Low (Max)	0.8 V
Input Logic Level - Low (Min)	0.12 V
Logic Type	NAND Gate
Max CL	50 pF
Max Propagation Delay	4.3 ns
Mounting Type	Surface Mount
Number of Circuits	4
Number of Inputs	2
Operating Temperature (Max)	125 °C
Operating Temperature (Min)	-40 °C
Package Length	0.173 in
Package Name	14-TSSOP
Package Width	4.4 mm
Qualification	AEC-Q100
Voltage - Supply (Maximum)	3.6 V
Voltage - Supply (Minimum)	1.2 V

74LVC00APW-Q100 Series

Quad 2-input NAND gate

Part	Current - Quiescent (Max)	Package Width	Package Name	Package Length	Logic Type	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Input Logic Level - High (Max)	Input Logic Level - High (Min)	Number of Circuits	Number of Inputs	Grade	Current - Output Low	Current - Output High	Operating Temperature (Max)	Operating Temperature (Min)	Max Propagation Delay	Max CL	Mounting Type	Input Logic Level - Low (Max)	Input Logic Level - Low (Min)	Qualification
Nexperia USA Inc. 74LVC00APW-Q100J	40 ĄA	4.4 mm	14-TSSOP	0.173 in	NAND Gate	1.2 V	3.6 V	2 V	1.08 V	4	2	Automotive	24 mA	24 mA	125 °C	-40 °C	4.3 ns	50 pF	Surface Mount	0.8 V	0.12 V	AEC-Q100

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

Datasheet

Footprint for wave soldering

Power considerations when using CMOS and BiCMOS logic devices

plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body

74LVC00APW-Q100 Nexperia Product Reliability

plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body

Nexperia package poster

Pin FMEA for LVC family

TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation