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LTC2267IUJ-12#TRPBF - 40 QFN

LTC2267IUJ-12#TRPBF

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Analog Devices

12-BIT, 105MSPS LOW POWER DUAL ADCS

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LTC2267IUJ-12#TRPBF - 40 QFN

LTC2267IUJ-12#TRPBF

Active
Analog Devices

12-BIT, 105MSPS LOW POWER DUAL ADCS

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationLTC2267IUJ-12#TRPBF
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceLVDS - Serial
FeaturesSimultaneous Sampling
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters2
Number of Bits12 bits
Number of Inputs2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case40-WFQFN Exposed Pad
Ratio - S/H:ADC1:1
Reference TypeExternal, Internal
Sampling Rate (Per Second)105 M
Supplier Device Package40-QFN (6x6)
Voltage - Supply, Analog [Max]1.9 V
Voltage - Supply, Analog [Min]1.7 V
Voltage - Supply, Digital [Max]1.9 V
Voltage - Supply, Digital [Min]1.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 2000$ 46.45

Description

General part information

LTC2267-12 Series

The LTC2268-12/LTC2267-12/LTC2266-12 are 2-channel, simultaneous sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 70.6dB SNR and 88dB spurious free dynamic range (SFDR). Ultralow jitter of 0.15psRMSallows undersampling of IF frequencies with excellent noise performance.DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS.The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity.The ENC+and ENC–inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.BitsLTC2267-1212LTC2267-1414ApplicationsCommunicationsCellular Base StationsSoftware Defined RadiosPortable Medical ImagingMultichannel Data AcquisitionNondestructive Testing