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CD54HC174F3A - CD54HC109F3A

CD54HC174F3A

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Texas Instruments

HIGH SPEED CMOS LOGIC HEX D-TYPE FLIP-FLOPS WITH RESET

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Search across all available documentation for this part.

DocumentsDatasheetCD54HC174, CD74HC174, CD54HCT174, CD74HCT174 datasheet (Rev. C)
CD54HC174F3A - CD54HC109F3A

CD54HC174F3A

Active
Texas Instruments

HIGH SPEED CMOS LOGIC HEX D-TYPE FLIP-FLOPS WITH RESET

Deep-Dive with AI

DocumentsDatasheetCD54HC174, CD74HC174, CD54HCT174, CD74HCT174 datasheet (Rev. C)
SpecificationsPricingSeriesDescriptionDocuments

Technical Specifications

Parameters and characteristics for this part

SpecificationCD54HC174F3A
Clock Frequency35 MHz
Current - Output High, Low5.2 mA, 5.2 mA
Current - Quiescent (Iq)8 ÁA
Input Capacitance10 pF
Max Propagation Delay @ V, Max CL28 ns
Mounting TypeThrough Hole
Number of Bits per Element6
Number of Elements [custom]1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 C
Output TypeNon-Inverted
Package / Case16-CDIP (0.300", 7.62mm)
Supplier Device Package16-CDIP
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

CD54HC174 Series

High Speed CMOS Logic Hex D-Type Flip-Flops with Reset

PartMax Propagation Delay @ V, Max CLTrigger TypeOperating Temperature [Min]Operating Temperature [Max]Current - Output High, LowOutput TypeCurrent - Quiescent (Iq)Supplier Device PackageNumber of Elements [custom]Mounting TypePackage / CaseInput CapacitanceClock FrequencyNumber of Bits per ElementTypeVoltage - Supply [Min]Voltage - Supply [Max]
Texas Instruments
CD54HC174F3A
The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174. The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174.
28 ns
Positive Edge
-55 C
125 °C
5.2 mA, 5.2 mA
Non-Inverted
8 ÁA
16-CDIP
1
Through Hole
16-CDIP (0.300", 7.62mm)
10 pF
35 MHz
6
D-Type
2 V
6 V

Description

General part information

CD54HC174 Series

The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state.

Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174.

The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state.