74LVC1G00QW5-7
ActiveNAND GATE, SINGLE, 2 INPUT, 5 PINS, SOT-25, 74LVC1G00Q
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74LVC1G00QW5-7
ActiveNAND GATE, SINGLE, 2 INPUT, 5 PINS, SOT-25, 74LVC1G00Q
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Technical Specifications
Parameters and characteristics for this part
| Specification | 74LVC1G00QW5-7 |
|---|---|
| Current - Output High, Low [x] | 32 mA |
| Current - Output High, Low [y] | 32 mA |
| Current - Quiescent (Max) [Max] | 4 µA |
| Grade | Automotive |
| Input Logic Level - High [Max] | 2 V |
| Input Logic Level - High [Min] | 1.7 V |
| Input Logic Level - Low [Max] | 0.8 V |
| Input Logic Level - Low [Min] | 0.7 V |
| Logic Type | NAND Gate |
| Max Propagation Delay @ V, Max CL | 5.5 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | SC-74A, SOT-753 |
| Qualification | AEC-Q100 |
| Supplier Device Package | SOT-25 |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.37 | |
| 10 | $ 0.28 | |||
| 25 | $ 0.24 | |||
| 100 | $ 0.16 | |||
| 250 | $ 0.13 | |||
| 500 | $ 0.10 | |||
| 1000 | $ 0.08 | |||
| Digi-Reel® | 1 | $ 0.37 | ||
| 10 | $ 0.28 | |||
| 25 | $ 0.24 | |||
| 100 | $ 0.16 | |||
| 250 | $ 0.13 | |||
| 500 | $ 0.10 | |||
| 1000 | $ 0.08 | |||
| Tape & Reel (TR) | 3000 | $ 0.07 | ||
| 6000 | $ 0.06 | |||
| 15000 | $ 0.06 | |||
| 30000 | $ 0.05 | |||
| 75000 | $ 0.05 | |||
| 150000 | $ 0.04 | |||
Description
General part information
74LVC1G00Q Series
The 74LVC1G00Q is an automotive compliant, single, 2-input positive NAND gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed-voltage environment. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.
Documents
Technical documentation and resources