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ADSP-21477BCPZ-1A

ADSP-21477BCPZ-1A

Unknown
Analog Devices Inc./Maxim Integrated

DSP, 200MHZ, LFCSP-VQ-EP-88, 115DEG C ROHS COMPLIANT: YES

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ADSP-21477BCPZ-1A

ADSP-21477BCPZ-1A

Unknown
Analog Devices Inc./Maxim Integrated

DSP, 200MHZ, LFCSP-VQ-EP-88, 115DEG C ROHS COMPLIANT: YES

Find alt

Description

General part information

ADSP-21477 Series

The fourth generation of SHARC®Processors, the ADSP-21477, includes low power floating point DSP products, which provide increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and 2M Bit on Chip SRAM, capable of supporting a single chip solution. All devices are code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21477 offers a very low power and high performance Processor – 200 MHz/1200 MFLOPs – in an 88-Ld LFCSP package. The low power architecture of the ADSP-21477 makes these products particularly well suited to address the automotive audio and industrial control market segments where low power is a requirement. In addition to its high core performance, the ADSP-21477 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation, ADSP-21477 SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

Technical Specifications

Parameters and characteristics for this part

SpecificationADSP-21477BCPZ-1A
Clock Rate (Frequency)200 MHz
InterfaceSPI, SPORT, DAI, UART/USART, I2C, DPI
Mounting TypeSurface Mount
On-Chip RAM2 Mbit
Operating Temperature (Max)85 °C
Operating Temperature (Min)-40 °C
Package / Case88-VFQFN Exposed Pad, CSP
Package Length12 mm
Package Name88-LFCSP-VQ
Package Width12 mm
TypeFloating Point
Voltage - Core1.2 V
Voltage - I/O3.3 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

ADSP-21477BCPZ-1A | Datasheet
EE-290: Managing the Core PLL on SHARC® Processors (Rev.5)
Package Drawing - 88-Lead LFCSP (12mm x 12mm w/ EP)
EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev.14)
ICE-1000/ICE-2000 Emulator User’s Guide (Rev.1.2)
EE-68: Analog Devices JTAG Emulation Technical Reference (Rev.10)
EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev.3)
SHARC®EZ-Extender®Manual (Rev.3.1)
VisualDSP++®5.0 Quick Installation Reference Card (Rev.3.1)
VisualDSP++®5.0 Product Release Bulletin (Rev.3.0)
EE-253: Power Bypass Decoupling of SHARC® Processors (Rev.1)
EE-264: Interfacing MultiMediaCard™ with ADSP-2126x SHARC® Processors (Rev.1)
Blackfin®/SHARC®USB EZ-Extender®Manual (Rev.1.1)
EE-210: SDRAM Selection and Configuration Guidelines for ADI Processors (Rev.2)
EE-260: Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC® Processors (Rev.1)
VisualDSP++®5.0 C/C++ Compiler Manual for SHARC®Processors (Rev.1.5)
VisualDSP++®5.0 Users Guide (Rev.3.0)
VisualDSP++®5.0 Assembler and Preprocessor Manual (Rev.3.4)
EE-355: Expert In-Circuit FLASH Programmer for SHARC® Processors (Rev.1)
EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev.1)
VisualDSP++®5.0 Kernel (VDK) Users Guide (Rev.3.5)
VisualDSP++®5.0 Loader and Utilities Manual (Rev.2.5)
EE-104: Setting Up Streams with the VisualDSP Debugger
SHARC®Audio EZ-Extender®Manual (Rev.1.1)
EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev.1)
EE-323: Implementing Dynamically Loaded Software Modules (Rev.1)
EE-232: Configuring the Signal Routing Unit of ADSP-2126x SHARC® DSPs (Rev.1)
EE-189: Link Port Tips & Tricks For ADSP-2106x & ADSP-2116x SHARC® DSPs
EE-177: SHARC® SPI Slave Booting (Rev.3)
VisualDSP++®5.0 Run-Time Library Manual for SHARC®Processors (Rev.1.5)
EE-286: Interfacing SDRAM Memories to SHARC® Processors (Rev.5)
EE-322: Expert Code Generator for SHARC® Processors (Rev.5)
VisualDSP++®5.0 Linker and Utilities Manual (Rev.3.5)
ADSP-21477/ADSP-21478/ADSP-21479 SHARC Anomaly List for Revisions 0.0, 0.1, 0.2 (Rev.I)
EE-348: Estimating Power for ADSP-214xx SHARC®Processors (Rev.4)
VisualDSP++®5.0 Licensing Guide (Rev.1.4)
ADSP-214xx SHARC®Processor Hardware Reference (Rev.1.1)
EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev.2)
VisualDSP++®5.0 Getting Started Guide (Rev.3.0)
ICE-100B Emulator User’s Guide (Rev.1.1)
EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev.1)
EE-340: Connecting SHARC®and Blackfin®Processors over SPI (Rev.1)
HPUSB, USB, and HPPCI Emulator User’s Guide (Rev.3.2)
SHARC®USB EZ-Extender®Manual (Rev.2.1)
ADSP-21477/ADSP-21478/ADSP-21479 SHARC Processor Data Sheet (Rev.E)
EE-332: Cycle Counting and Profiling (Rev.2)