CY7C1380KV33-167AXI is a pipelined SRAM that integrates with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (active low CE1), depth-expansion chip enables (active low CE2 and CE3), burst control inputs (ADSC, ADSP, and active low ADV), write enables (active low BWX, and active low BWE), and global write (active low GW). Asynchronous inputs include the output enable (active low OE) and the ZZ pin. Address and chip enable is registered at rising edge of clock when address strobe processor (active low ADSP) or address strobe controller (active low ADSC) is active. Subsequent burst address can be internally generated as this is controlled by the advance pin (active low ADV).