
LTC2273CUJ#PBF
Active16-BIT, 80MSPS SERIAL OUTPUT ADC (JESD204)
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LTC2273CUJ#PBF
Active16-BIT, 80MSPS SERIAL OUTPUT ADC (JESD204)
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Technical Specifications
Parameters and characteristics for this part
| Specification | LTC2273CUJ#PBF |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | JESD204 |
| Features | PGA |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 1 |
| Number of Bits | 16 |
| Number of Inputs | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 40-WFQFN Exposed Pad |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 80 M |
| Supplier Device Package | 40-QFN (6x6) |
| Voltage - Supply, Analog [Max] | 3.465 V |
| Voltage - Supply, Analog [Min] | 3.135 V |
| Voltage - Supply, Digital [Max] | 3.465 V |
| Voltage - Supply, Digital [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 61 | $ 85.48 | |
Description
General part information
LTC2273 Series
The LTC2273/LTC2272 are 80Msps/65Msps, 16-bit A/D converters with a high speed serial interface. They are designed for digitizing high frequency, wide dynamic range signals with an input bandwidth of 700MHz. The input range of the ADC can be optimized using the PGA front end. The output data is serialized according to the JEDEC serial interface for data converters specification (JESD204).The LTC2273/LTC2272 are perfect for demanding applications where it is desirable to isolate the sensitive analog circuits from the noisy digital logic. The AC performance includes a 77.7dB Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low internal jitter of 80fs RMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±4.5LSB INL and ±1LSB DNL (no missing codes) over temperature.The encode clock inputs, ENC+and ENC–, may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.ApplicationsTelecommunicationsReceiversCellular Base StationsSpectrum AnalysisImaging SystemsATE
Documents
Technical documentation and resources