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Description

General part information

ADSP-21489 Series

The SHARC ADSP-21489 is one of two new members of the fourth generation ofSHARC®Processorsthat now includes theADSP-21483,ADSP-21486,ADSP-21487,ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21489 offers the highest performance–450 MHz/2700 MFLOPs–in an LQFP package within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21489 particularly well suited to address the automotive audio and industrial control segments. In addition to its high core performance, the ADSP-21489 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, IDP, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as SPI,UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

Technical Specifications

Parameters and characteristics for this part

SpecificationADSP-21489BSWZ-4A
Clock Rate (Frequency)400 MHz
InterfaceI2C, SPORT, UART/USART, EBI/EMI, DAI, SPI
Mounting TypeSurface Mount
Non-Volatile Memory TypeExternal
On-Chip RAM5 Mbit
Operating Temperature (Max)85 °C
Operating Temperature (Min)-40 °C
Package / Case100-LQFP Exposed Pad
Package Length14 mm
Package Name100-LQFP-EP
Package Width14 mm
TypeFloating Point
Voltage - Core1.1 V
Voltage - I/O3.3 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

Datasheet
ADSP-21489BSWZ-4A | Datasheet
EE-290: Managing the Core PLL on SHARC® Processors (Rev.5)
EE-110: A Quick Primer on ELF and DWARF File Formats
EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev.1)
VisualDSP++®5.0 Run-Time Library Manual for SHARC®Processors (Rev.1.5)
EE-355: Expert In-Circuit FLASH Programmer for SHARC® Processors (Rev.1)
EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev.3)
VisualDSP++®5.0 Kernel (VDK) Users Guide (Rev.3.5)
VisualDSP++®5.0 Product Release Bulletin (Rev.3.0)
EE-348: Estimating Power for ADSP-214xx SHARC®Processors (Rev.4)
EE-189: Link Port Tips & Tricks For ADSP-2106x & ADSP-2116x SHARC® DSPs
EE-340: Connecting SHARC®and Blackfin®Processors over SPI (Rev.1)
EE-322: Expert Code Generator for SHARC® Processors (Rev.5)
Package Drawing - 100-Lead LQFP (14mm x 14mm w/ heatsink)
EE-260: Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC® Processors (Rev.1)
VisualDSP++®5.0 Getting Started Guide (Rev.3.0)
ADSP-21483/21486/21487/21488/21489 SHARC Anomaly List for Revisions 0.2, 0.3 (Rev.L)
EE-286: Interfacing SDRAM Memories to SHARC® Processors (Rev.5)
ADSP-214xx SHARC®Processor Hardware Reference (Rev.1.1)
Blackfin®/SHARC®USB EZ-Extender®Manual (Rev.1.1)
SHARC®Audio EZ-Extender®Manual (Rev.1.1)
HPUSB, USB, and HPPCI Emulator User’s Guide (Rev.3.2)
SHARC®EZ-Extender®Manual (Rev.3.1)
VisualDSP++®5.0 Licensing Guide (Rev.1.4)
EE-128: DSP in C++: Calling Assembly Class Member Functions From C++
VisualDSP++®5.0 C/C++ Compiler Manual for SHARC®Processors (Rev.1.5)
EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev.1)
EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev.1)
EE-210: SDRAM Selection and Configuration Guidelines for ADI Processors (Rev.2)
ADSP-21489 EZ-KIT Lite®Evaluation System Manual (Rev.1.1)
VisualDSP++®5.0 Quick Installation Reference Card (Rev.3.1)
VisualDSP++®5.0 Loader and Utilities Manual (Rev.2.5)
EE-357: Static Voltage Scaling for ADSP-2148x SHARC® Processors (Rev.1)
EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev.2)
EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev.14)
EE-68: Analog Devices JTAG Emulation Technical Reference (Rev.10)
ICE-100B Emulator User’s Guide (Rev.1.1)
EE-346: Using the On-Chip Thermal Diode on Analog Devices Processors (Rev.2)
SHARC®USB EZ-Extender®Manual (Rev.2.1)
EE-232: Configuring the Signal Routing Unit of ADSP-2126x SHARC® DSPs (Rev.1)
VisualDSP++®5.0 Assembler and Preprocessor Manual (Rev.3.4)
EE-323: Implementing Dynamically Loaded Software Modules (Rev.1)
EE-104: Setting Up Streams with the VisualDSP Debugger
VisualDSP++®5.0 Users Guide (Rev.3.0)
EE-332: Cycle Counting and Profiling (Rev.2)
EE-352: Soldering Considerations for Exposed-Pad Packages (Rev.1)
EE-264: Interfacing MultiMediaCard™ with ADSP-2126x SHARC® Processors (Rev.1)
EE-177: SHARC® SPI Slave Booting (Rev.3)
VisualDSP++®5.0 Linker and Utilities Manual (Rev.3.5)
EE-253: Power Bypass Decoupling of SHARC® Processors (Rev.1)
ICE-1000/ICE-2000 Emulator User’s Guide (Rev.1.2)