
UPD48576118F1-E18-DW1-A
Active576M-BIT LOW LATENCY DRAM SEPARATE I/O
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UPD48576118F1-E18-DW1-A
Active576M-BIT LOW LATENCY DRAM SEPARATE I/O
Deep-Dive with AI
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Distributor | Package | Quantity | $ | |
---|---|---|---|---|
Digikey | Bulk | 4 | $ 75.64 |
Description
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UPD48576118F1-E18-DW1-A Series
The µPD48576118F1 is a 33, 554, 432 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell. The µPD48576118F1 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and CK#. These products are suitable for application which require synchronous operation, High-Speed, low voltage, high density and wide bit configuration.
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