74AUP2G79DC,125

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Nexperia

FLIP FLOP D-TYPE POS-EDGE PUSH-PULL 2-ELEMENT AUTOMOTIVE 8-PIN VSSOP T/R

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DocumentsDatasheet 74AUP2G79DC Nexperia Product Reliability +8

74AUP2G79DC,125

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Nexperia

FLIP FLOP D-TYPE POS-EDGE PUSH-PULL 2-ELEMENT AUTOMOTIVE 8-PIN VSSOP T/R

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DocumentsDatasheet 74AUP2G79DC Nexperia Product Reliability +8

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	74AUP2G79DC,125

Clock Frequency	309 MHz
Current - Output High, Low [custom]	4 mA
Current - Output High, Low [custom]	4 mA
Function	Standard
Input Capacitance	0.6 pF
Max Propagation Delay @ V, Max CL	5.8 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Non-Inverted
Package / Case	8-VFSOP
Package / Case [y]	2.3 mm
Package / Case [y]	0.091 in
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	0.8 V

74AUP2G79 Series

Low-power dual D-type flip-flop; positive-edge trigger

Part	Number of Bits per Element	Input Capacitance	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Max Propagation Delay @ V, Max CL	Trigger Type	Type	Function	Package / Case [y]	Package / Case	Package / Case [y]	Output Type	Number of Elements	Clock Frequency	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Operating Temperature [Min]	Operating Temperature [Max]
Nexperia 74AUP2G79DC,125	1	0.6 pF	4 mA	4 mA	5.8 ns	Positive Edge	D-Type	Standard	2.3 mm	8-VFSOP	0.091 in	Non-Inverted	2	309 MHz	0.8 V	3.6 V	Surface Mount	-40 °C	125 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Arrow	N/A	5	$ 0.37
Digikey	Bulk	1998	$ 0.15

Description

General part information

74AUP2G79 Series

The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Documents

Technical documentation and resources

Datasheet

plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body

Package information

plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body

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74AUP2G79DC,125

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74AUP2G79DC,125

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Technical Specifications

74AUP2G79 Series

Pricing

Description

74AUP2G79 Series

Documents

Datasheet

74AUP2G79DC Nexperia Product Reliability

Pin FMEA for AUP family

VSSOP8; Reel pack for SMD, 7''; Q3/T4 product orientation

Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904

Nexperia package poster

PicoGate Logic footprints

Low-power dual D-type flip-flop; positive-edge trigger

plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body

plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body

Technical Specifications

74AUP2G79 Series