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SN74LVC1G00MDCKREP - SC70-5

SN74LVC1G00MDCKREP

Active
Texas Instruments

ENHANCED PRODUCT SINGLE 1-INPUT, 1.65-V TO 5.5-V NAND GATE

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SN74LVC1G00MDCKREP - SC70-5

SN74LVC1G00MDCKREP

Active
Texas Instruments

ENHANCED PRODUCT SINGLE 1-INPUT, 1.65-V TO 5.5-V NAND GATE

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationSN74LVC1G00MDCKREPSN74LVC1G00-EP Series
Current - Output High, Low [custom]32 mA32 mA
Current - Output High, Low [custom]32 mA32 mA
Current - Quiescent (Max) [Max]10 µA10 µA
Input Logic Level - High [Max]2 V2 V
Input Logic Level - High [Min]1.7 V1.7 V
Input Logic Level - Low [Max]0.8 V0.8 V
Input Logic Level - Low [Min]0.7 V0.7 V
Logic TypeNAND GateNAND Gate
Max Propagation Delay @ V, Max CL5 ns4 - 5 ns
Mounting TypeSurface MountSurface Mount
Number of Circuits11
Number of Inputs22
Operating Temperature [Max]125 °C85 - 125 °C
Operating Temperature [Min]-55 °C-55 - -40 °C
Package / Case5-TSSOP, SOT-353, SC-70-55-TSSOP, SOT-353, SC-70-5, SOT-753, SC-74A
Supplier Device PackageSC-70-5SC-70-5, SOT-23-5
Voltage - Supply [Max]5.5 V5.5 V
Voltage - Supply [Min]1.65 V1.65 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

SN74LVC1G00-EP Series

Enhanced product single 1-input, 1.65-V to 5.5-V NAND gate

PartMounting TypeMax Propagation Delay @ V, Max CLLogic TypeCurrent - Quiescent (Max) [Max]Number of InputsInput Logic Level - Low [Max]Input Logic Level - Low [Min]Voltage - Supply [Max]Voltage - Supply [Min]Current - Output High, Low [custom]Current - Output High, Low [custom]Input Logic Level - High [Min]Input Logic Level - High [Max]Package / CaseNumber of CircuitsOperating Temperature [Min]Operating Temperature [Max]Supplier Device Package
Texas Instruments
V62/04732-02XE
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Surface Mount
5 ns
NAND Gate
10 µA
2
0.8 V
0.7 V
5.5 V
1.65 V
32 mA
32 mA
1.7 V
2 V
5-TSSOP, SC-70-5, SOT-353
1
-55 °C
125 °C
SC-70-5
Texas Instruments
SN74LVC1G00IDCKREP
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Surface Mount
4 ns
NAND Gate
10 µA
2
0.8 V
0.7 V
5.5 V
1.65 V
32 mA
32 mA
1.7 V
2 V
5-TSSOP, SC-70-5, SOT-353
1
-40 °C
85 °C
SC-70-5
Texas Instruments
SN74LVC1G00MDBVREP
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Surface Mount
5 ns
NAND Gate
10 µA
2
0.8 V
0.7 V
5.5 V
1.65 V
32 mA
32 mA
1.7 V
2 V
SC-74A, SOT-753
1
-55 °C
125 °C
SOT-23-5
Texas Instruments
SN74LVC1G00MDCKREP
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Surface Mount
5 ns
NAND Gate
10 µA
2
0.8 V
0.7 V
5.5 V
1.65 V
32 mA
32 mA
1.7 V
2 V
5-TSSOP, SC-70-5, SOT-353
1
-55 °C
125 °C
SC-70-5

Description

General part information

SN74LVC1G00-EP Series

This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation.

The SN74LVC1G00 performs the Boolean function Y =A • Bor Y =A+Bin positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Documents

Technical documentation and resources

How to Select Little Logic (Rev. A)

Application note

Little Logic Guide 2018 (Rev. G)

Selection guide

Design Summary for WCSP Little Logic (Rev. B)

Product overview

Selecting the Right Level Translation Solution (Rev. A)

Application note

Logic Guide (Rev. AB)

Selection guide

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

SN74LVC1G00-EP datasheet (Rev. D)

Data sheet

LOGIC Pocket Data Book (Rev. B)

User guide

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Application note

Understanding Advanced Bus-Interface Products Design Guide

Application note

Input and Output Characteristics of Digital Integrated Circuits

Application note

Standard Linear & Logic for PCs, Servers & Motherboards

More literature

Low-Voltage Logic (LVC) Designer's Guide

Design guide

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Application note

Live Insertion

Application note

Signal Switch Data Book (Rev. A)

User guide

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note

LVC Characterization Information

Application note

CMOS Power Consumption and CPD Calculation (Rev. B)

Application note

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

More literature

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

User guide

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Application note

Texas Instruments Little Logic Application Report

Application note

TI IBIS File Creation, Validation, and Distribution Processes

Application note

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Application note