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LTC2263IUJ-12#TRPBF
Integrated Circuits (ICs)

LTC2263IUJ-12#TRPBF

Active
Analog Devices Inc./Maxim Integrated

12-BIT, 25MSPS LOW POWER DUAL ADCS

LTC2263IUJ-12#TRPBF
Integrated Circuits (ICs)

LTC2263IUJ-12#TRPBF

Active
Analog Devices Inc./Maxim Integrated

12-BIT, 25MSPS LOW POWER DUAL ADCS

Technical Specifications

Parameters and characteristics for this part

SpecificationLTC2263IUJ-12#TRPBF
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceLVDS - Serial
FeaturesSimultaneous Sampling
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters2 count
Number of Bits12 bits
Number of Inputs2
Operating Temperature (Max)85 °C
Operating Temperature (Min)-40 °C
Package / Case40-WFQFN Exposed Pad
Package Length6 mm
Package Name40-QFN
Package Width6 mm
Ratio - ADC1
Ratio - S/H1
Reference TypeExternal, Internal
Sampling Rate (Per Second)25 MHz
Voltage - Supply, Analog (Max)1.9 V
Voltage - Supply, Analog (Min)1.7 V
Voltage - Supply, Digital (Max)1.9 V
Voltage - Supply, Digital (Min)1.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$Updated
DigikeyTape & Reel (TR) 2000$ 34.101w

CAD

3D models and CAD resources for this part

Description

General part information

LTC2263-12 Series

The LTC2265-12/LTC2264-12/LTC2263-12 are 2-channel, simultaneous sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 71dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.15psRMSallows undersampling of IF frequencies with excellent noise performance.DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS.The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity.The ENC+and ENC–inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.BitsLTC2263-1212LTC2263-1414ApplicationsCommunicationsCellular Base StationsSoftware Defined RadiosPortable Medical ImagingMultichannel Data AcquisitionNondestructive Testing

Documents

Technical documentation and resources