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NUCLEO-H7S3L8 - NUCLEO-H7S3L8

NUCLEO-H7S3L8

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STMicroelectronics

STM32 NUCLEO-144 DEVELOPMENT BOARD WITH STM32H7S3L8 MCU, SMPS, SUPPORTS ARDUINO, ST ZIO AND MORPHO CONNECTIVITY

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NUCLEO-H7S3L8 - NUCLEO-H7S3L8

NUCLEO-H7S3L8

Active
STMicroelectronics

STM32 NUCLEO-144 DEVELOPMENT BOARD WITH STM32H7S3L8 MCU, SMPS, SUPPORTS ARDUINO, ST ZIO AND MORPHO CONNECTIVITY

Deep-Dive with AI

Documents+10

Technical Specifications

Parameters and characteristics for this part

SpecificationNUCLEO-H7S3L8
Board TypeEvaluation Platform
ContentsBoard(s)
Core ProcessorARM® Cortex®-M7
Interconnect SystemST Zio, Arduino R3 Shield, ST Morpho
Mounting TypeFixed
PlatformNucleo-144
Suggested Programming EnvironmentSTM32Cube, Keil MDK, IAR EW
TypeMCU 32-Bit
Utilized IC / PartSTM32H7S3L8

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyBulk 1$ 35.00
NewarkEach 1$ 36.40

Description

General part information

NUCLEO-H7S3L8 Series

STM32H7Sxx8 devices are based on the high-performance Arm®Cortex®-M7 32-bit RISC core operating at up to 600 MHz. The Cortex -M7 core features a floating point unit (FPU) which supports Arm double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of instruction cache and 32 Kbytes of data cache. STM32H7Sxx8 devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.

STM32H7Sxx8 devices incorporate high-speed embedded memories, 64 Kbytes of user flash memory and 128 Kbytes of system flash memory,and up to 620 Kbytes of RAM (including 128 Kbytes that can be shared between ITCM and AXI, including 64 Kbytes exclusively ITCM, including 128 Kbyte DTCM, including 64 Kbytes exclusively DTCM, including 32 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. To improve application robustness, all memories feature error code correction (one error correction, two error detections).

The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC coprocessor for trigonometric functions). All the devices offer two ADCs, a low-power RTC, 4 general-purpose 32-bit timers, 7 general-purpose 16-bit timers including one PWM timer for motor control, five low-power timers, and a cryptographic acceleration cell (CRYP), Public key acceleration (PKA), a secure AES coprocessor (SAES) and a memory cipher engine (MCE) The devices support one digital filter for external sigma-delta modulators or digital microphone with voice activity detection. They also feature standard and advanced communication interfaces.