
9DB106BFILFT
Obsolete6-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN2

9DB106BFILFT
Obsolete6-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN2
Description
General part information
9DB106 Series
The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.
Technical Specifications
Parameters and characteristics for this part
| Specification | 9DB106BFILFT |
|---|---|
| Differential Input | Yes |
| Differential Output | Yes |
| Frequency - Max | 105 MHz |
| Input | Clock |
| Input Ratio | 1 |
| Main Purpose | PCI Express (PCIe) |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Output | HCSL |
| Output Ratio | 6 |
| Package Length | 0.209 in |
| Package Name | 28-SSOP |
| Package Width | 5.3 mm |
| PLL | Yes |
| Voltage - Supply (Maximum) | 3.465 V |
| Voltage - Supply (Minimum) | 3.135 V |
Pricing
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CAD
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Documents
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