
STM32F411VET6U
ActiveIC MCU 32BIT 512KB FLASH 100LQFP
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STM32F411VET6U
ActiveIC MCU 32BIT 512KB FLASH 100LQFP
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Technical Specifications
Parameters and characteristics for this part
| Specification | STM32F411VET6U |
|---|---|
| Connectivity | MMC/SD/SDIO, LINbus, IrDA, USB OTG, SPI, I2C, UART/USART |
| Core Processor | ARM® Cortex®-M4 |
| Core Size | 32-Bit Single-Core |
| Data Converters [custom] | 16 |
| Data Converters [custom] | 12 b |
| Mounting Type | Surface Mount |
| Number of I/O | 81 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | Internal |
| Package / Case | 100-LQFP |
| Peripherals | Brown-out Detect/Reset, DMA, POR, WDT, PWM, I2S |
| Program Memory Size | 512 KB |
| Program Memory Type | FLASH |
| RAM Size | 128 K |
| Speed | 100 MHz |
| Supplier Device Package | 100-LQFP (14x14) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
STM32F411CE Series
The STM32F411xC/xE devices are based on the high-performance Arm®Cortex®-M4 32-bit RISC core operating at a frequency of up to 100 MHz. The Cortex®-M4 core features a floating-point unit (FPU) single precision, which supports all Arm single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU), which enhances application security.
The STM32F411xC/xE belongs to the STM32 Dynamic Efficiency product line (with products combining power efficiency, performance and integration) while adding a new innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power consumption during data batching.
The STM32F411xC/xE incorporate high-speed embedded memories (up to 512 Kbytes of flash memory, 128 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB bus and a 32-bit multi-AHB bus matrix.
Documents
Technical documentation and resources