
ADN2804ACPZ
Unknown622 MBPS CLOCK AND DATA RECOVERY IC WITH INTEGRATED LIMITING AMPLIFIER

ADN2804ACPZ
Unknown622 MBPS CLOCK AND DATA RECOVERY IC WITH INTEGRATED LIMITING AMPLIFIER
Description
General part information
ADN2804 Series
The ADN2804 provides the receiver functions of quantization, signal level detect, clock and data recovery, and data retiming for 622 Mbps NRZ data. The ADN2804 automatically locks to 622 Mbps data without the need for an external reference clock or programming. In the absence of input data, the output clock drifts no more than ±5%. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver.The receiver’s front-end loss-of-signal (LOS) detector circuit indicates when the input signal level falls below a user-adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output.The ADN2804 is available in a compact 5 mm × 5 mm, 32-lead LFCSP.ApplicationsBPON ONTSONET OC-12WDM transpondersRegenerators/repeatersTest equipmentBroadband cross-connects and routers
Technical Specifications
Parameters and characteristics for this part
| Specification | ADN2804ACPZ |
|---|---|
| Differential Input | Yes |
| Differential Output | Yes |
| Frequency - Max | 622 MHz |
| Input | CML |
| Input Ratio | 1 |
| Main Purpose | SONET/SDH |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Output | LVDS |
| Output Ratio | 2 |
| Package / Case | 32-WFQFN Exposed Pad, CSP |
| Package Length | 5 mm |
| Package Name | 32-LFCSP-WQ |
| Package Width | 5 mm |
| PLL | Yes |
| Voltage - Supply (Maximum) | 3.6 V |
| Voltage - Supply (Minimum) | 3 V |
Pricing
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