TC2320TG-G
ActiveN/P-CHANNEL ENHANCEMENT-MODE DUAL MOSFET
Deep-Dive with AI
Search across all available documentation for this part.
TC2320TG-G
ActiveN/P-CHANNEL ENHANCEMENT-MODE DUAL MOSFET
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | TC2320TG-G |
|---|---|
| Configuration | N and P-Channel |
| Drain to Source Voltage (Vdss) | 200 V |
| Input Capacitance (Ciss) (Max) @ Vds | 110 pF, 125 pF |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 150 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 8-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Rds On (Max) @ Id, Vgs | 7 Ohm |
| Supplier Device Package | 8-SOIC |
| Technology | MOSFET (Metal Oxide) |
| Vgs(th) (Max) @ Id | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.93 | |
| 25 | $ 1.62 | |||
| 100 | $ 1.47 | |||
| Digi-Reel® | 1 | $ 1.93 | ||
| 25 | $ 1.62 | |||
| 100 | $ 1.47 | |||
| Tape & Reel (TR) | 3300 | $ 1.47 | ||
| Microchip Direct | T/R | 1 | $ 1.93 | |
| 25 | $ 1.62 | |||
| 100 | $ 1.47 | |||
| 1000 | $ 1.43 | |||
| 5000 | $ 1.40 | |||
TC2320 Series
N/P-Channel Enhancement-Mode Dual MOSFET
| Part | Vgs(th) (Max) @ Id | Package / Case | Package / Case [y] | Package / Case [x] | Operating Temperature [Min] | Operating Temperature [Max] | Technology | Mounting Type | Drain to Source Voltage (Vdss) | Configuration | Rds On (Max) @ Id, Vgs | Input Capacitance (Ciss) (Max) @ Vds | Supplier Device Package |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Microchip Technology TC2320TG-G | 2 V | 8-SOIC | 3.9 mm | 0.154 in | -55 °C | 150 °C | MOSFET (Metal Oxide) | Surface Mount | 200 V | N and P-Channel | 7 Ohm | 110 pF, 125 pF | 8-SOIC |
Description
General part information
TC2320 Series
TC2320 consists of a high voltage, low threshold N- and P-channel MOSFET in an 8-Lead SOIC package. This low threshold enhancement-mode (normally-off) transistor utilizes an advanced vertical DMOS structure and well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.
Vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
Documents
Technical documentation and resources