Zenode.ai Logo
AD9577BCPZ-RL

AD9577BCPZ-RL

Active
Analog Devices Inc./Maxim Integrated

CLOCK GENERATOR 19.44MHZ TO 27MHZ-IN 637.5MHZ-OUT 40-PIN LFCSP EP T/R

Find alt
AD9577BCPZ-RL

AD9577BCPZ-RL

Active
Analog Devices Inc./Maxim Integrated

CLOCK GENERATOR 19.44MHZ TO 27MHZ-IN 637.5MHZ-OUT 40-PIN LFCSP EP T/R

Find alt

Description

General part information

AD9577 Series

The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. The PLLs have I2C programmable output frequencies and formats. The fractional-N PLL can support spread spectrum clocking for reduced EMI radiated peak power. Both PLLs can support frequency margining. Other applications with demanding phase noise and jitter requirements can benefit from this part.The first integer-N PLL section (PLL1) consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), a programmable feedback divider, and two independently programmable output dividers. By connecting an external crystal or applying a reference clock to the REFCLK pin, frequencies of up to 637.5 MHz can be synchronized to the input reference. Each output divider and feedback divider ratio is I2C programmed for the required output rates.A second fractional-N PLL (PLL2) with a programmable modulus allows VCO frequencies that are fractional multiples of the reference frequency to be synthesized. Each output divider and feedback divider ratio can be programmed for the required output rates, up to 637.5 MHz. This fractional-N PLL can also operate in integer-N mode for the lowest jitter.Up to four differential output clock signals can be configured as either LVPECL or LVDS signaling formats. Alternatively, the outputs can be configured for up to eight CMOS outputs. Combinations of these formats are supported. No external loop filter components are required, thus conserving valuable design time and board space. The AD9577 is available in a 40-lead, 6 mm × 6 mm LFCSP package and can operate from a single 3.3 V supply. The operating temperature range is −40°C to +85°C.ApplicationsLow jitter, low phase noise multioutput clock generator for data communications applications including Ethernet, Fibre Channel, SONET, SDH, PCI-e, SATA, PTN, OTN, ADC/DAC, and digital videoSpread spectrum clocking

Technical Specifications

Parameters and characteristics for this part

SpecificationAD9577BCPZ-RL
Differential InputNo
Differential OutputYes
Frequency - Max637.5 MHz
InputClock, Crystal
Input Ratio2
Main PurposeSONET/SDH, Ethernet, PCI Express (PCIe)
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature (Max)85 °C
Operating Temperature (Min)-40 °C
OutputLVCMOS, LVPECL, LVDS
Output Ratio5
Package / Case40-WFQFN Exposed Pad, CSP
Package Length6 mm
Package Name40-LFCSP-WQ
Package Width6 mm
PLLYes
Voltage - Supply (Maximum)3.6 V
Voltage - Supply (Minimum)3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Sign in to see pricing

Create a free account to access distributor pricing data.

CAD

3D models and CAD resources for this part