74LVC86APW,118

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Nexperia USA Inc.

LOGIC IC, XOR (EXCLUSIVE OR), QUAD, 2 INPUTS, 14 PINS, TSSOP, 74LVC86

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74LVC86APW,118

Active

Nexperia USA Inc.

LOGIC IC, XOR (EXCLUSIVE OR), QUAD, 2 INPUTS, 14 PINS, TSSOP, 74LVC86

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Description Specifications Series Pricing CAD Documents

Description

General part information

74LVC86APW Series

The 74LVC86A is a quad 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Technical Specifications

Parameters and characteristics for this part

Specification	74LVC86APW,118

Current - Output High	24 mA
Current - Output Low	24 mA
Current - Quiescent (Max)	40 ĄA
Input Logic Level - High (Max)	2 V
Input Logic Level - High (Min)	1.07 V
Input Logic Level - Low (Max)	0.8 V
Input Logic Level - Low (Min)	0.58 V
Logic Type	XOR (Exclusive OR)
Max CL	50 pF
Max Propagation Delay	5 ns
Mounting Type	Surface Mount
Number of Circuits	4
Number of Inputs	2
Operating Temperature (Max)	125 °C
Operating Temperature (Min)	-40 °C
Package Length	0.173 in
Package Name	14-TSSOP
Package Width	4.4 mm
Voltage - Supply (Maximum)	3.6 V
Voltage - Supply (Minimum)	1.2 V

74LVC86APW Series

Quad 2-input EXCLUSIVE-OR gate

Part	Max Propagation Delay	Max CL	Input Logic Level - High (Max)	Input Logic Level - High (Min)	Current - Quiescent (Max)	Mounting Type	Current - Output Low	Current - Output High	Package Name	Input Logic Level - Low (Max)	Input Logic Level - Low (Min)	Package Width	Package Length	Logic Type	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Number of Circuits	Number of Inputs	Operating Temperature (Max)	Operating Temperature (Min)
Nexperia USA Inc. 74LVC86APW,118	5 ns	50 pF	2 V	1.07 V	40 ĄA	Surface Mount	24 mA	24 mA	14-TSSOP	0.8 V	0.58 V	4.4 mm	0.173 in	XOR (Exclusive OR)	1.2 V	3.6 V	4	2	125 °C	-40 °C

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

Datasheet

TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation

plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body

plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body

Power considerations when using CMOS and BiCMOS logic devices

Nexperia package poster

Footprint for wave soldering

74LVC86APW Nexperia Product Reliability

Pin FMEA for LVC family