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Description

General part information

71V124 Series

The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.

Technical Specifications

Parameters and characteristics for this part

Specification71V124SA15PHG
Access Time15 ns
Memory Depth128 K
Memory FormatSRAM
Memory Interface (Type)Parallel
Memory Size1 Mbit
Memory TypeVolatile
Memory Width8 bit
Mounting TypeSurface Mount
Operating Temperature (Max)70 °C
Operating Temperature (Min)0 °C
Package Length10.16 mm
Package Name32-TSOP II, 32-SOIC
Package Width10.16 mm
TechnologySRAM - Asynchronous
Voltage - Supply (Maximum)3.6 V
Voltage - Supply (Minimum)3 V
Write Cycle Time - Page15 ns
Write Cycle Time - Word15 ns

Pricing

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