ZL30612LDG6
ActiveCLOCK GENERATOR 0.0000005MHZ TO 900MHZ-IN 900MHZ-OUT 100-PIN QFN TRAY
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ZL30612LDG6
ActiveCLOCK GENERATOR 0.0000005MHZ TO 900MHZ-IN 900MHZ-OUT 100-PIN QFN TRAY
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | ZL30612LDG6 | ZL30612 Series |
|---|---|---|
| - | - | |
| Differential - Input:Output [custom] | True | True |
| Differential - Input:Output [custom] | True | True |
| Input | HCSL, LVDS, LVCMOS, LVPECL | HCSL, LVDS, LVCMOS, LVPECL |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Circuits | 1 | 1 |
| Output | CMOS | CMOS |
| Package / Case | 100-VQFN Dual Rows, Exposed Pad | 100-VQFN Dual Rows, Exposed Pad |
| PLL | True | True |
| Ratio - Input:Output | 6:10 | 6:10 |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
ZL30612 Series
2-Ch SyncE Line Card Synchronizer
| Part | Ratio - Input:Output | Number of Circuits | Output | PLL | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Package / Case | Input | Mounting Type |
|---|---|---|---|---|---|---|---|---|---|
Microchip Technology ZL30612LDG6 | |||||||||
Microchip Technology ZL30612LDG6 | 6:10 | 1 | CMOS | 100-VQFN Dual Rows, Exposed Pad | HCSL, LVCMOS, LVDS, LVPECL | Surface Mount |
Description
General part information
ZL30612 Series
[ZL30642B](https://www.microchip.com/en-us/product/ZL30642B) is recommended as the replacement for new designs.
The ZL30612 offers two DPLL channels of Synchronous Ethernet (SyncE) clock translation. Fourth generation timing technology provides one third the jitter of the previous generation devices with a 40% smaller footprint. Excellent jitter performance makes this device ideally suited for SyncE/Sonet/SDH timing and line card applications needing to support 10G/40G and 100G PHYs. Features supported include hitless reference switching between active and redundant timing cards, frequency translation from backplane clock to frequencies required by PHY devices, jitter filtering, and holdover in case both active and redundant timing cards fail.
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Documents
Technical documentation and resources
No documents available