SN74AUC1G74 Series

Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Catalog

Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Part	Max Propagation Delay @ V, Max CL [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Number of Elements	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type	Number of Bits per Element	Supplier Device Package	Clock Frequency	Output Type	Current - Quiescent (Iq)	Function	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Type	Input Capacitance	Trigger Type	Package / Case	Package / Case [y]	Package / Case [y]
Texas Instruments SN74AUC1G74DCTR	1.8 ns	85 °C	-40 °C	1	2.7 V	0.8 V	Surface Mount	1	SM8	275 MHz	Complementary	10 µA	Reset Set(Preset)	9 mA	9 mA	D-Type	2.5 pF	Positive Edge
Texas Instruments SN74AUC1G74YZTR
Texas Instruments SN74AUC1G74YZPR	1.8 ns	85 °C	-40 °C	1	2.7 V	0.8 V	Surface Mount	1	8-DSBGA	275 MHz	Complementary	10 µA	Reset Set(Preset)	9 mA	9 mA	D-Type	2.5 pF	Positive Edge	8-XFBGA DSBGA
Texas Instruments SN74AUC1G74DCURE4	1.8 ns	85 °C	-40 °C	1	2.7 V	0.8 V	Surface Mount	1		275 MHz	Complementary	10 µA	Reset Set(Preset)	9 mA	9 mA	D-Type	2.5 pF	Positive Edge	8-VFSOP	2.3 mm	0.091 in
Texas Instruments SN74AUC1G74RSER	1.8 ns	85 °C	-40 °C	1	2.7 V	0.8 V	Surface Mount	1	8-UQFN (1.5x1.5)	275 MHz	Complementary	10 µA	Reset Set(Preset)	9 mA	9 mA	D-Type	2.5 pF	Positive Edge	8-UFQFN

Catalog

Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Key Features

• Available in the Texas Instruments NanoFree™ PackageOptimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub-1-V OperableMax tpdof 1.5 ns at 1.8 VLow Power Consumption, 10-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)NanoFree Is a trademark of Texas InstrumentsAvailable in the Texas Instruments NanoFree™ PackageOptimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub-1-V OperableMax tpdof 1.5 ns at 1.8 VLow Power Consumption, 10-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)NanoFree Is a trademark of Texas Instruments

Description

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, theCLRinput overrides thePREinput when they are both low. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, theCLRinput overrides thePREinput when they are both low. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.