Zenode.ai Logo

74ALS74 Series

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset

Manufacturer: Texas Instruments

Catalog(3 parts)

PartCurrent - Output High, LowCurrent - Output High, LowCurrent - Quiescent (Iq)Number of Bits per ElementMax Propagation Delay @ V, Max CLOperating TemperatureOperating TemperatureMounting TypeOutput TypeFunctionNumber of ElementsClock FrequencyTypeTrigger TypePackage / CasePackage / CasePackage / CaseVoltage - SupplyVoltage - Supply
Texas Instruments
SN74ALS74AD
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154", 3.90mm Width)
0.00800000037997961 A
0.00039999998989515007 A
0.004000000189989805 A
1 ul
1.7999999712969842e-8 s
70 °C
0 °C
Surface Mount
Complementary
Reset, Set(Preset)
2 ul
34000000 Hz
D-Type
Positive Edge
0.003899999894201755 m
0.003911599982529879 m
14-SOIC
5.5 V
4.5 V
Texas Instruments
SN74ALS74ADRE4
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154", 3.90mm Width)
0.00800000037997961 A
0.00039999998989515007 A
0.004000000189989805 A
1 ul
1.7999999712969842e-8 s
70 °C
0 °C
Surface Mount
Complementary
Reset, Set(Preset)
2 ul
34000000 Hz
D-Type
Positive Edge
0.003899999894201755 m
0.003911599982529879 m
14-SOIC
5.5 V
4.5 V
Texas Instruments
SN74ALS74AN
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-DIP (0.300", 7.62mm)
0.00800000037997961 A
0.00039999998989515007 A
0.004000000189989805 A
1 ul
1.7999999712969842e-8 s
70 °C
0 °C
Through Hole
Complementary
Reset, Set(Preset)
2 ul
34000000 Hz
D-Type
Positive Edge
0.007619999814778566 m
0.007619999814778566 m
14-DIP
5.5 V
4.5 V

Key Features

Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPsPackage Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

Description

AI
These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C. These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.