74LVC74 Series

Dual D-type flip-flop with set and reset; positive-edge trigger

Catalog

Dual D-type flip-flop with set and reset; positive-edge trigger

Part	Number of Elements	Number of Bits per Element	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Function	Max Propagation Delay	Max CL	Mounting Type	Clock Frequency	Package Width	Package Name	Package Length	Trigger Type	Type	Input Capacitance	Operating Temperature (Max)	Operating Temperature (Min)	Current - Output Low	Current - Output High	Current - Quiescent (Iq)	Output Type	Package / Case	Qualification	Grade
Nexperia USA Inc. 74LVC74AD,118	2	1 bits	1.2 V	3.6 V	Set(Preset) and Reset	5.2 ns	50 pF	Surface Mount	150 MHz	3.9 mm	14-SO 14-SOIC	0.154 in	Positive Edge	D-Type	4 pF	125 °C	-40 °C	24 mA	24 mA	10 µA	Complementary
Nexperia USA Inc. 74LVC74ABQ-Q100X	2	1 bits	1.2 V	3.6 V	Set(Preset) and Reset	5.2 ns	50 pF	Surface Mount	150 MHz	3 mm	14-DHVQFN	2.5 mm	Positive Edge	D-Type	4 pF	125 °C	-40 °C	24 mA	24 mA	10 µA	Complementary	14-VFQFN Exposed Pad	AEC-Q100	Automotive
Nexperia USA Inc. 74LVC74APW,118	2	1 bits	1.2 V	3.6 V	Set(Preset) and Reset	5.2 ns	50 pF	Surface Mount	150 MHz	4.4 mm	14-TSSOP	0.173 in	Positive Edge	D-Type	4 pF	125 °C	-40 °C	24 mA	24 mA	10 µA	Complementary
Nexperia USA Inc. 74LVC74ADB,112	2	1 bits	1.2 V	3.6 V	Set(Preset) and Reset	5.2 ns	50 pF	Surface Mount	150 MHz	5.3 mm	14-SSOP	0.209 in	Positive Edge	D-Type	4 pF	125 °C	-40 °C	24 mA	24 mA	10 µA	Complementary
Nexperia USA Inc. 74LVC74AD-Q100J	2	1 bits	1.2 V	3.6 V	Set(Preset) and Reset	5.2 ns	50 pF	Surface Mount	150 MHz	3.9 mm	14-SO 14-SOIC	0.154 in	Positive Edge	D-Type	4 pF	125 °C	-40 °C	24 mA	24 mA	10 µA	Complementary		AEC-Q100	Automotive
Nexperia USA Inc. 74LVC74AD,112	2	1 bits	1.2 V	3.6 V	Set(Preset) and Reset	5.2 ns	50 pF	Surface Mount	150 MHz	3.9 mm	14-SO 14-SOIC	0.154 in	Positive Edge	D-Type	4 pF	125 °C	-40 °C	24 mA	24 mA	10 µA	Complementary

Catalog

Dual D-type flip-flop with set and reset; positive-edge trigger

Description

The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQoutputs.