SN65LVDS93B-Q1 Series

10MHz – 135MHz 28-bit Flat Panel Display Link LVDS SerDes Transmitter

Catalog

10MHz – 135MHz 28-bit Flat Panel Display Link LVDS SerDes Transmitter

Part	Package / Case	Package / Case	Package / Case	Supplier Device Package	Output Type	Number of Inputs	Data Rate	Voltage - Supply [Max]	Voltage - Supply [Min]	Operating Temperature [Max]	Operating Temperature [Min]	Number of Outputs	Mounting Type	Input Type	Function	Qualification	Grade
Texas Instruments SN65LVDS93BDGG	6.1 mm	0.24 in	56-TFSOP	56-TSSOP	LVDS	28	2.38 Gbps	3.6 V	3 V	85 °C	-40 °C	4	Surface Mount	LVTTL	Serializer/Deserializer
Texas Instruments SN65LVDS93ADGG	6.1 mm	0.24 in	56-TFSOP	56-TSSOP	LVDS	28	3.78 Gbps	3.6 V	3 V	85 °C	-40 °C	4	Surface Mount	LVTTL	Serializer
Texas Instruments SN65LVDS93DGGR	6.1 mm	0.24 in	56-TFSOP	56-TSSOP	LVDS	28	1.904 Gbps	3.6 V	3 V	85 °C	-40 °C	4	Surface Mount	LVTTL	Serializer
Texas Instruments SN65LVDS93DGGG4	6.1 mm	0.24 in	56-TFSOP	56-TSSOP	LVDS	28	1.904 Gbps	3.6 V	3 V	85 °C	-40 °C	4	Surface Mount	LVTTL	Serializer
Texas Instruments SN65LVDS93BIDGGRQ1	6.1 mm	0.24 in	56-TFSOP	56-TSSOP	LVDS	28	2.38 Gbps	3.6 V	3 V	85 °C	-40 °C	4	Surface Mount	LVTTL	Serializer/Deserializer	AEC-Q100	Automotive
Texas Instruments SN65LVDS93AIDGGRQ1	6.1 mm	0.24 in	56-TFSOP	56-TSSOP	LVDS	28	135 Mbps	3.6 V	3 V	85 °C	-40 °C	4	Surface Mount	LVTTL	Serializer	AEC-Q100	Automotive
Texas Instruments SN65LVDS93BDGGR	6.1 mm	0.24 in	56-TFSOP	56-TSSOP	LVDS	28	2.38 Gbps	3.6 V	3 V	85 °C	-40 °C	4	Surface Mount	LVTTL	Serializer/Deserializer

Catalog

10MHz – 135MHz 28-bit Flat Panel Display Link LVDS SerDes Transmitter

Key Features

• AEC-Q100 Qualified for Automotive ApplicationsTemperature Grade 3: –40°C to 85°CHBM ESD Classification 3CDM ESD Classification C6LVDS Display Series Interfaces Directly to LCD Display Panels With Integrated LVDSPackage: 14-mm x 6.1-mm TSSOP1.8-V Up to 3.3-V Tolerant Data Inputs to Connect Directly to Low-Power, Low-Voltage Application and Graphic ProcessorsTransfer Rate up to 85 Mpps (Mega Pixel Per Second); Pixel Clock Frequency Range 10 MHz to 85 MHz; Max 2.38 Gbps data rate supportedSuited for Display Resolutions Ranging From HVGA up to HD With Low EMIOperates From a Single 3.3-V Supply and 170 mW (Typical) at 75 MHz28 Data Channels Plus Clock in Low-Voltage TTL to 4 Data Channels Plus Clock Out Low-Voltage DifferentialConsumes Less Than 1 mW When DisabledSelectable Rising or Falling Clock Edge Triggered InputsSupport Spread Spectrum Clocking (SSC)Supports RGB 888 to LVDS I ConversionAEC-Q100 Qualified for Automotive ApplicationsTemperature Grade 3: –40°C to 85°CHBM ESD Classification 3CDM ESD Classification C6LVDS Display Series Interfaces Directly to LCD Display Panels With Integrated LVDSPackage: 14-mm x 6.1-mm TSSOP1.8-V Up to 3.3-V Tolerant Data Inputs to Connect Directly to Low-Power, Low-Voltage Application and Graphic ProcessorsTransfer Rate up to 85 Mpps (Mega Pixel Per Second); Pixel Clock Frequency Range 10 MHz to 85 MHz; Max 2.38 Gbps data rate supportedSuited for Display Resolutions Ranging From HVGA up to HD With Low EMIOperates From a Single 3.3-V Supply and 170 mW (Typical) at 75 MHz28 Data Channels Plus Clock in Low-Voltage TTL to 4 Data Channels Plus Clock Out Low-Voltage DifferentialConsumes Less Than 1 mW When DisabledSelectable Rising or Falling Clock Edge Triggered InputsSupport Spread Spectrum Clocking (SSC)Supports RGB 888 to LVDS I Conversion

Description

The SN65LVDS93A-Q1 FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS94 and LCD panels with integrated LVDS receiver. When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The SN65LVDS93A-Q1 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN).SHTDNis an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level. The SN65LVDS93A-Q1 is characterized for operation over ambient air temperatures of –40°C to 85°C. The SN65LVDS93A-Q1 FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS94 and LCD panels with integrated LVDS receiver. When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The SN65LVDS93A-Q1 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN).SHTDNis an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level. The SN65LVDS93A-Q1 is characterized for operation over ambient air temperatures of –40°C to 85°C.