Catalog
Translator, Dual Differential LVPECL to LVTTL
Key Features
• 2.0ns Typical Propagation Delay
• Maximum Frequency > 180 MHz
• Differential LVPECL Inputs
• PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with GND= 0 V
• 24 mA LVTTL Outputs
• Flow Through Pinouts
• Internal Pulldown Resistors
• Q Output will default LOW with inputs open or at GND
• ESD Protection: >1.5 KV HBM, >100 V MM
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
• Transistor Count = 91 devices
• Pb-Free Packages are Available
Description
AI
The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the LVELT23 makes it ideal for applications which require the translation of a clock and a data signal.The LVELT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBBreference, the LVELT23 does not require both ECL standard versions. The LVPECL inputs are differential; there is no specified difference between the differential input 10H and 100K standards. Therefore, the MC100LVELT23 can accept any standard differential LVPECL input referenced from a VCCof 3.3V.