Catalog
2-Ch SyncE Network Synchronizer
Key Features
- Two independent clock channels
- Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure
- Ultra-fast lock to GPS/GNSS and 1PPS for faster power-up time for 4G LTE, 5G & Wireless Infrastructure
- Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems
- Split oscillator option lowers cost, lowers jitter, and provides redundancy
- Fully compliant to EEC (G.8262), SEC (G.813), GR-253 SMC and GR-1244 Stratum 3
- Excellent jitter performance of 240 fs RMS in the 12 kHz to 20 MHz band meets jitter requirements for 10G/40G and 100G PHYs
- Two programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 1045 MHz
- One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz
- 8 differential or 16 single ended ultra-low jitter outputs plus two general purpose CMOS outputs
- Programmable output advancement/delay to accommodate trace delays or compensate for system routing paths
- Up to three programmable digital PLLs/NCOs with loop bandwidth from 0.1 mHz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
- Accepts up to 10 differential or 10 single ended input references
- Full reference monitoring of electrical failures
- Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
- Any input reference can be fed with clock, sync (frame pulse), clock /sync pair
- Easy Configuration and dynamic programming via SPI/I2C interface
- Factory programming available
- Operates from a single crystal resonator or clock oscillator
Description
AI
The ZL30672 offers 2 channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, this device offers new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make this device ideal for use in chassis based systems with active and redundant timing cards as well as in single board ("pizza box") applications where a timing device needs to have features of both a timing and a line card PLL.
Log in to your [MyMicrochip](https://login.microchip.com/ssologin/Account/Login?ReturnUrl=%2Fssologin%2Fconnect%2Fauthorize%2Fcallback%3Fclient_id%3DAuthenticatedUserapi%26redirect_uri%3Dhttps%253A%252F%252Fwww.microchip.com%252Fmymicrochip%252F%2523%252Fcallback%26response_type%3Dcode%26scope%3Dopenid%2520profile%2520AuthenticatedUserapi%26state%3Dd0743a67132a4f7cabf87766498ef7a5%26code_challenge%3D7VwT2FZLyz0rJZj7k5oY1o1voVEo9eQaaVmfjNzodVQ%26code_challenge_method%3DS256%26response_mode%3Dquery) account (with SDE enabled) and request for data sheet and the following application notes.
AN3467 Crystals and Oscillators for Next Generation Timing Solutions
ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices
ZLAN-656 Redwood PSNR
ZLAN-664 Board Design Recommendations for Redwood
ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood
ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package
ZLAN-724 Phase Measurement Compensation for Redwood
ZLAN-728 Indirect Read and Write Procedure