Catalog
6-Output Clock Generator ext. EEPROM
Key Features
- The two APLLs have fractional dividers and integer dividers to make four independent frequency families
- Four Flexible Input Clocks: One crystal/CMOS input, Two differential/CMOS inputs, One single-ended/CMOS input
- Any input frequency from 9.72MHz to 1.25GHz (300MHz max for CMOS)
- Activity monitors, automatic or manual switching
- Glitch-less clock switching by pin or register
- 6 Any-Frequency, Any-Format Outputs
- Any output frequency from 1Hz to 1045MHz
- High-resolution frac-N APLL with 0ppm error
- Output jitter from integer multiply and dividers as low as 0.17ps RMS (12kHz-20MHz)
- Output jitter from fractional dividers is typically < 1ps RMS, many frequencies <0.5ps RMS
- Each output has an independent divider and is configurable as LVDS, LVPECL, HCSL, 2xCMOS or HSTL
- In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)
- Multiple output supply voltage banks with CMOS output voltages from 1.5V to 3.3V
- Precise output alignment circuitry and per-output phase adjustment
- Per-output enable/disable and glitch-less start/stop (stop high or low)
- Automatic self-configuration at power-up from external EEPROM (see ZL30265 for internal EEPROM); up to 8 configurations pin-selectable
- External feedback for zero-delay applications
- Numerically controlled oscillator mode
- Spread-spectrum modulation mode
- Generates PCIe 1, 2, 3, 4, 5 & 6 compliant clocks
- Easy-to-configure design requires no external VCXO or loop filter components
- SPI or I2C processor Interface
- Core supply voltage options: 2.5V only, 3.3V only, 1.8V+2.5V or 1.8V+3.3V
- Space-saving 8x8mm QFN56 (0.5mm pitch)
Description
AI
The miClockSynth ZL30264 high-performance, any-rate multiplier and clock generator simplifies board design by generating ultra-low-jitter clock signals from a single crystal or crystal oscillator while generating additional independent frequency families.
With up to four independent frequency families on one chip, best-in-class jitter performance, and two fractional-N APLLs with both a fractional and integer divider, the ZL30264 creates a complete clock-tree, improving design reliability, reducing bill of materials (BOM) cost, and simplifying design by replacing multiple crystals and peripheral timing components.