9112-17 Series

High Performance Low Skew 9 Output Clock

Manufacturer: Renesas Electronics Corporation

Catalog

High Performance Low Skew 9 Output Clock

Part	Multiplier	Divider	Output Ratio	Input Ratio	Frequency - Max	Operating Temperature (Max)	Mounting Type	Package Name	Input	Package Width	Package Length	Type	PLL	Differential Output	Differential Input	Output	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Number of Circuits
Renesas Electronics Corporation 9112AF-17LFT	No	No	9	1	133 MHz	70 °C	Surface Mount	16-QSOP 16-SSOP	Clock	3.9 mm	0.154 in	Zero Delay Buffer	Yes with Bypass	No	No	Clock	5.5 V	2.97 V	1
Renesas Electronics Corporation 9112BF-17LF	No	No	9	1	133 MHz	70 °C	Surface Mount	16-QSOP 16-SSOP	Clock	3.9 mm	0.154 in	Zero Delay Buffer	Yes with Bypass	No	No	Clock	5.5 V	2.97 V	1
Renesas Electronics Corporation 9112AM-17LF	No	No	9	1	133 MHz	70 °C	Surface Mount	16-SOIC	Clock	3.9 mm	0.154 in	Zero Delay Buffer	Yes with Bypass	No	No	Clock	5.5 V	2.97 V	1
Renesas Electronics Corporation 9112BM-17LF	No	No	9	1	133 MHz	70 °C	Surface Mount	16-SOIC	Clock	3.9 mm	0.154 in	Zero Delay Buffer	Yes with Bypass	No	No	Clock	5.5 V	2.97 V	1
Renesas Electronics Corporation 9112AM-17LFT	No	No	9	1	133 MHz	70 °C	Surface Mount	16-SOIC	Clock	3.9 mm	0.154 in	Zero Delay Buffer	Yes with Bypass	No	No	Clock	5.5 V	2.97 V	1
Renesas Electronics Corporation 9112BF-17LFT	No	No	9	1	133 MHz	70 °C	Surface Mount	16-QSOP 16-SSOP	Clock	3.9 mm	0.154 in	Zero Delay Buffer	Yes with Bypass	No	No	Clock	5.5 V	2.97 V	1
Renesas Electronics Corporation 9112BM-17LFT	No	No	9	1	133 MHz	70 °C	Surface Mount	16-SOIC	Clock	3.9 mm	0.154 in	Zero Delay Buffer	Yes with Bypass	No	No	Clock	5.5 V	2.97 V	1
Renesas Electronics Corporation 9112AF-17LF	No	No	9	1	133 MHz	70 °C	Surface Mount	16-QSOP 16-SSOP	Clock	3.9 mm	0.154 in	Zero Delay Buffer	Yes with Bypass	No	No	Clock	5.5 V	2.97 V	1

Catalog

High Performance Low Skew 9 Output Clock

Description

The IDT9112-17 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz.