Catalog
Dual Channel Any-to-Any Translator and JA
Key Features
- Two Independent Channels
•
• Input Clocks (Per Channel)* Three inputs, two differential/CMOS, one CMOS
• * Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS)
• * Inputs continually monitored for activity and frequency accuracy
• * Automatic or manual reference switching
•
• Low-Bandwidth DPLL (Per Channel)* Programmable Bandwidth, 5Hz to 500Hz
• * Attenuates jitter up to several UI
• * Free-Run or holdover on loss of all inputs
• * Hitless reference switching
• * High-resolution holdover averaging
• * Digitally controlled phase adjustment
•
• Low-Jitter Fractional-N APLL and 3 Outputs (Per Channel)* Any output frequency from <1Hz to 1035MHz
• * High-resolution fractional frequency conversion with 0ppm error
• * Easy-to-configure, encapsulated design requires no external VCXO or loop filter components
• * Each output has independent dividers
• * Output jitter is typically 0.16 to 0.28ps RMS (12kHz-20MHz integration band)
• * Each output is CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL
• * In 2xCMOS mode the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)
• * Per-output supply pin with CMOS output voltages from 1.5V to 3.3V
• * Precise output alignment circuitry and per-output phase adjustment
• * Per-output enable/disable and glitchless start/stop (stop high or low)
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• General Features* Automatic self-configuration at power-up from Internal EEPROM; up to four pin selectable configurations
• * Numerically controlled oscillator mode
• * Zero-delay mode with external feedback
• * SPI or I2C processor interface
• * Easy-to-use evaluation software
• * Industrial temperature range -40 to +85°C
• * 64 pin 5 x 10mm LGA Package
Description
AI
[CREATE AND SAMPLE YOUR CUSTOM ZL30182 HERE](https://clockworks.microchip.com/microchip/design/inputZL)
The ZL30182 is a dual channel high performance OTN clock translator that provides output clocks with jitter performance of 250fs RMS. The device integrates dual, independent digital phase locked loops (DPLLs), dual analog PLLs and EEPROM. With programmable loop bandwidth from 5Hz to 500 Hz the DPLL provides hitless reference switching, holdover and jitter filtering. The integrated APLLs generate the ultra-low jitter output clocks programmable to any frequency from <1Hz to 1035MHz. The integrated EEPROM provides automatic self-configuration of the device at start-up.