Catalog(4 parts)
| Part | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Number of Circuits | Package / Case▲▼ | Package / Case | Package / Case▲▼ | Mounting Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Logic Type | Supplier Device Package | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
3.5999999046325684 V | 1.649999976158142 V | 16-Bit | 0.006099999882280827 m | 48-TFSOP | 0.006095999851822853 m | Surface Mount | -40 °C | 85 °C | Universal Bus Driver | 48-TSSOP | 0.012000000104308128 A | 0.012000000104308128 A | |
3.5999999046325684 V | 1.649999976158142 V | 16-Bit | 48-TFSOP | Surface Mount | -40 °C | 85 °C | Universal Bus Driver | 0.012000000104308128 A | 0.012000000104308128 A | ||||
3.5999999046325684 V | 1.649999976158142 V | 16-Bit | 48-BSSOP (0.295", 7.50mm Width) | Surface Mount | -40 °C | 85 °C | Universal Bus Driver | 48-SSOP | 0.012000000104308128 A | 0.012000000104308128 A | |||
3.5999999046325684 V | 1.649999976158142 V | 16-Bit | 48-BSSOP (0.295", 7.50mm Width) | Surface Mount | -40 °C | 85 °C | Universal Bus Driver | 48-SSOP | 0.012000000104308128 A | 0.012000000104308128 A |
Key Features
• Member of the Texas Instruments Widebus™ FamilyEPIC™ (Enhanced-Performance Implanted CMOS) Submicron ProcessOutput Port Has Equivalent 26-Series Resistors, So No External Resistors Are RequiredDesigned to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM SpecificationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA Per JESD 17Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsPackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) PackagesNOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.Widebus, EPIC are trademarks of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyEPIC™ (Enhanced-Performance Implanted CMOS) Submicron ProcessOutput Port Has Equivalent 26-Series Resistors, So No External Resistors Are RequiredDesigned to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM SpecificationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA Per JESD 17Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsPackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) PackagesNOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.Widebus, EPIC are trademarks of Texas Instruments.
Description
AI
This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
The output port includes equivalent 26-series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162334 is characterized for operation from –40°C to 85°C.
This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
The output port includes equivalent 26-series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162334 is characterized for operation from –40°C to 85°C.