SN74ALVCH162334 Series

16-Bit Universal Bus Driver With 3-State Outputs

Catalog

16-Bit Universal Bus Driver With 3-State Outputs

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Mounting Type	Package / Case	Package / Case	Package / Case [custom]	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Logic Type	Number of Circuits	Package / Case [y]	Package / Case [y]
Texas Instruments SN74ALVCH162334GR	12 mA	12 mA	Surface Mount	48-TFSOP	0.24 in	6.1 mm	48-TSSOP	1.65 V	3.6 V	85 °C	-40 °C	Universal Bus Driver	16-Bit
Texas Instruments SN74ALVCH162334VR	12 mA	12 mA	Surface Mount	48-TFSOP	0.173 in 4.4 mm			1.65 V	3.6 V	85 °C	-40 °C	Universal Bus Driver	16-Bit
Texas Instruments SN74ALVCH162334DL	12 mA	12 mA	Surface Mount	48-BSSOP			48-SSOP	1.65 V	3.6 V	85 °C	-40 °C	Universal Bus Driver	16-Bit	0.295 in	7.5 mm
Texas Instruments SN74ALVCH162334DLR	12 mA	12 mA	Surface Mount	48-BSSOP			48-SSOP	1.65 V	3.6 V	85 °C	-40 °C	Universal Bus Driver	16-Bit	0.295 in	7.5 mm

Catalog

16-Bit Universal Bus Driver With 3-State Outputs

Key Features

• Member of the Texas Instruments Widebus™ FamilyEPIC™ (Enhanced-Performance Implanted CMOS) Submicron ProcessOutput Port Has Equivalent 26-Series Resistors, So No External Resistors Are RequiredDesigned to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM SpecificationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA Per JESD 17Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsPackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) PackagesNOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.Widebus, EPIC are trademarks of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyEPIC™ (Enhanced-Performance Implanted CMOS) Submicron ProcessOutput Port Has Equivalent 26-Series Resistors, So No External Resistors Are RequiredDesigned to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM SpecificationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA Per JESD 17Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsPackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) PackagesNOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.Widebus, EPIC are trademarks of Texas Instruments.

Description

This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation. Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state. The output port includes equivalent 26-series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162334 is characterized for operation from –40°C to 85°C. This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation. Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state. The output port includes equivalent 26-series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162334 is characterized for operation from –40°C to 85°C.