SN74AVCH16T245 Series

16-Bit Dual Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs

Catalog

16-Bit Dual Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs

Part	Supplier Device Package	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Mounting Type	Number of Elements	Logic Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Output Type	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Number of Bits per Element	Package / Case	Package / Case [custom]
Texas Instruments SN74AVCH16T245GQLR	56-BGA Microstar Junior (7x4.5)	12 mA	12 mA	Surface Mount	2	Translation Transceiver	1.2 V	3.6 V	3-State	56-VFBGA	85 °C	-40 °C	8
Texas Instruments 74AVCH16T245DGG-P	48-TSSOP	12 mA	12 mA	Surface Mount	2	Translation Transceiver	0.8 V	3.6 V	3-State	48-TFSOP	85 °C	-40 °C	8	0.24 in	6.1 mm
Texas Instruments SN74AVCH16T245GR	48-TSSOP	12 mA	12 mA	Surface Mount	2	Translation Transceiver	1.2 V	3.6 V	3-State	48-TFSOP	85 °C	-40 °C	8	0.24 in	6.1 mm

Catalog

16-Bit Dual Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs

Key Features

• VCCIsolation Feature – If Either VCCInput is at GND, Both Ports are in the High-Impedance StateControl Inputs VIH/VILLevels Are Referenced to VCCAVoltageOvervoltage-Tolerant Inputs and Outputs Allow Mixed Voltage-Mode Data CommunicationsFully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2 V to 3.6 V Power-Supply RangeIoffSupports Partial-Power-Down Mode OperationI/Os are 4.6 V TolerantBus Hold on Data Inputs Eliminates the Need for External Pullup and Pulldown ResistorsMaximum Data Rates380 Mbps (1.8 V to 3.3 V Level-Shifting)200 Mbps (<1.8 V to 3.3 V Level-Shifting)200 Mbps (Level-Shifting to 2.5 V or 1.8 V)150 Mbps (Level-Shifting to 1.5 V)100 Mbps (Level-Shifting to 1.2 V)Latch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 228000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)VCCIsolation Feature – If Either VCCInput is at GND, Both Ports are in the High-Impedance StateControl Inputs VIH/VILLevels Are Referenced to VCCAVoltageOvervoltage-Tolerant Inputs and Outputs Allow Mixed Voltage-Mode Data CommunicationsFully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2 V to 3.6 V Power-Supply RangeIoffSupports Partial-Power-Down Mode OperationI/Os are 4.6 V TolerantBus Hold on Data Inputs Eliminates the Need for External Pullup and Pulldown ResistorsMaximum Data Rates380 Mbps (1.8 V to 3.3 V Level-Shifting)200 Mbps (<1.8 V to 3.3 V Level-Shifting)200 Mbps (Level-Shifting to 2.5 V or 1.8 V)150 Mbps (Level-Shifting to 1.5 V)100 Mbps (Level-Shifting to 1.2 V)Latch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 228000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVCH16T245 device is optimized to operate with VCCA/VCCBset at 1.4 V to 3.6 V. The device is operational with VCCA/VCCBas low as 1.2 V. The A port is designed to track VCCA. VCCAaccepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCBaccepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes. The SN74AVCH16T245 control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This device is fully specified for partial-power-down applications using Ioff. The VCCisolation feature ensures that if either VCCinput is at GND, then both ports are in the high-impedance state. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74AVCH16T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated. This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVCH16T245 device is optimized to operate with VCCA/VCCBset at 1.4 V to 3.6 V. The device is operational with VCCA/VCCBas low as 1.2 V. The A port is designed to track VCCA. VCCAaccepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCBaccepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes. The SN74AVCH16T245 control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This device is fully specified for partial-power-down applications using Ioff. The VCCisolation feature ensures that if either VCCinput is at GND, then both ports are in the high-impedance state. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74AVCH16T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.