Catalog
Octal Transparent D-Type Latch with 3-State Outputs
Key Features
• Supply Voltage Range from 1.65V to 3.6V
• Sinks or Sources 24mA at VCC = 3V
• CMOS Low Power Consumption
• IOFF Supports Partial-Power Down Operation
• Inputs or Outputs Accept Up to 5.5V
• Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed VoltageApplications
• Schmitt Trigger Action at All Inputs
• Typical VOLP (Quiet Output Ground Bounce) less than 0.8V withVCC = 3.3V and TA = +25°C
• Typical VOHV (Quiet Output Dynamic VOH) greater than 2.0Vwith VCC = 3.3V and TA = +25°C
• ESD Protection Tested per JESD 22Exceeds 200-V Machine Model (A115)Exceeds 2000-V Human Body Model (A114)Exceeds 1000-V Charged Device Model (C101)
• Exceeds 200-V Machine Model (A115)
• Exceeds 2000-V Human Body Model (A114)
• Exceeds 1000-V Charged Device Model (C101)
• Latch-Up Exceeds 250mA per JESD 78, Class I
• All devices are:Totally Lead-Free & Fully RoHS compliant (Notes 1 & 2)Halogen and Antimony Free. "Green" Device (Note 3)
• Totally Lead-Free & Fully RoHS compliant (Notes 1 & 2)
• Halogen and Antimony Free. "Green" Device (Note 3)
Description
AI
The 74LVC573A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.OEdoes not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.