74LV132 Series

Quad 2-input NAND Schmitt trigger

Catalog

Quad 2-input NAND Schmitt trigger

Part	Logic Type	Input Logic Level - High (Min)	Input Logic Level - High (Max)	Number of Inputs	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Number of Circuits	Operating Temperature (Max)	Operating Temperature (Min)	Mounting Type	Package Name	Current - Output High	Current - Output Low	Input Logic Level - Low (Max)	Input Logic Level - Low (Min)	Current - Quiescent (Max)	Features	Package Width	Package Length	Max Propagation Delay	Max CL	Qualification	Grade
Nexperia USA Inc. 74LV132DB,118	NAND Gate	1.4 V	3.9 V	2	1 V	5.5 V	4	125 °C	-40 °C	Surface Mount	14-SSOP	12 mA	12 mA	1.2 V	0.3 V	40 ĄA	Schmitt Trigger	5.3 mm	0.209 in	9 ns	50 pF
Nexperia USA Inc. 74LV132D,118	NAND Gate	1.4 V	3.9 V	2	1 V	5.5 V	4	125 °C	-40 °C	Surface Mount	14-SO 14-SOIC	12 mA	12 mA	1.2 V	0.3 V	40 ĄA	Schmitt Trigger	3.9 mm	0.154 in	9 ns	50 pF
Nexperia USA Inc. 74LV132DB,112	NAND Gate	1.4 V	3.9 V	2	1 V	5.5 V	4	125 °C	-40 °C	Surface Mount	14-SSOP	12 mA	12 mA	1.2 V	0.3 V	40 ĄA	Schmitt Trigger	5.3 mm	0.209 in	9 ns	50 pF
Nexperia USA Inc. 74LV132PW,112	NAND Gate	1.4 V	3.9 V	2	1 V	5.5 V	4	125 °C	-40 °C	Surface Mount	14-TSSOP	12 mA	12 mA	1.2 V	0.3 V	40 ĄA	Schmitt Trigger	4.4 mm	0.173 in	8.8 ns	50 pF
Nexperia USA Inc. 74LV132D-Q100J	NAND Gate	1.4 V	3.9 V	2	1 V	5.5 V	4	125 °C	-40 °C	Surface Mount	14-SO 14-SOIC	12 mA	12 mA	1.2 V	0.3 V	20 µA	Schmitt Trigger	3.9 mm	0.154 in	9 ns	50 pF	AEC-Q100	Automotive
Nexperia USA Inc. 74LV132PW-Q100J	NAND Gate	1.4 V	3.9 V	2	1 V	5.5 V	4	125 °C	-40 °C	Surface Mount	14-TSSOP	12 mA	12 mA	1.2 V	0.3 V	20 µA	Schmitt Trigger	4.4 mm	0.173 in	9 ns	50 pF	AEC-Q100	Automotive
Nexperia USA Inc. 74LV132PW,118	NAND Gate	1.4 V	3.9 V	2	1 V	5.5 V	4	125 °C	-40 °C	Surface Mount	14-TSSOP	12 mA	12 mA	1.2 V	0.3 V	40 ĄA	Schmitt Trigger	4.4 mm	0.173 in	9 ns	50 pF

Catalog

Quad 2-input NAND Schmitt trigger

Description

The 74LV132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.