74ALVC74 Series

Dual D-type flip-flop with set and reset; positive-edge trigger

Manufacturer: Nexperia

Catalog

Dual D-type flip-flop with set and reset; positive-edge trigger

Part	Mounting Type	Number of Elements	Output Type	Clock Frequency	Package / Case [x]	Package / Case [y]	Package / Case	Trigger Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Function	Current - Output High, Low	Current - Quiescent (Iq)	Max Propagation Delay @ V, Max CL	Operating Temperature [Max]	Operating Temperature [Min]	Number of Bits per Element	Input Capacitance	Type
Nexperia 74ALVC74D,118	Surface Mount	2	Complementary	425 MHz	0.154 in	3.9 mm	14-SOIC	Positive Edge	1.65 V	3.6 V	14-SO	Reset, Set(Preset)	24 mA	10 µA	3.8 ns	85 °C	-40 °C	1	3.5 pF	D-Type

Catalog

Dual D-type flip-flop with set and reset; positive-edge trigger

Key Features

• Wide supply voltage range from 1.65 V to 3.6 V

• CMOS low power dissipation

• Overvoltage tolerant inputs to 3.6 V

• Direct interface with TTL levels

• IOFFcircuitry provides partial Power-down mode operation

• Latch-up performance exceeds 250 mA per JESD78 Class II.A

• Complies with JEDEC standard:

• JESD8-7 (1.65 to 1.95 V)

• JESD8-5 (2.3 to 2.7 V)

• JESD8C/JESD36 (2.7 V to 3.6 V)

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Description

The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q andQoutputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.