Catalog
100 MHz Secure DSC with Integrated HSM
Key Features
• Operating Conditions* 3.0 V to 3.6 V
• * -40ºC to +125ºC, DC to 100 MHz
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• dsPIC33CK DSC Core* Up to 512 KBytes of Program Flash with ECC and Live Update (dual-partition Flash)
• * Up to 64 KBytes of Data SRAM with Memory Built in Self-Test (MBIST)
• * Firmware attestation
• * Code efficient (C and Assembly) CPU architecture designed for real-time applications
• * 4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
• * Single-cycle, mixed-sign 32-bit MUL
• * Fast 6-cycle hardware 32/16 and 16/16 DIV
• * Dual 40-bit fixed point Accumulators (ACC) for DSP operations
• * Single-cycle MAC/MPY with dual data fetch and result write-back
• * Zero overhead looping support
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• Security Features* Integrated secure subsystem with isolation as per the HSM security architecture
• * EVITA Full compliant secure subsystem
• * Secure key storage
• * Secure Subsystem with Advanced Crypto Engine (ACE) for execution of various cryptography commands
• * Fast Crypto Engine for SHA-256, HMAC and AES-CMAC algorithms
• * Sign/verify support using ECDSA – P224, P256, P384 and 256-bit Brainpool elliptic curves
• * Sign/verify support using ECDSA – SECP256K1 (bitcoin/blockchain) curve
• * RSA 2048-bit signature generation and verification
• * RSA 3072-bit signature verification only
• * Elliptic Curve Diffie-Hellman (ECDH) key agreement support for P224, P256, P384 and 256-bit Brainpool
• * Elliptic Curve Burmeiseter-Desmedt (ECBD) key agreement support for P224 curve
• * Internal symmetric and asymmetric key generation and derivation: P224, P256, P384 and 256-bit Brainpool; 2048-bit RSA keys; AES 16-byte keys
• * AES encryption/decryption supporting AES ECB/GCM modes
• * RSA 1024-bit and 2048-bit keys encryption/decryption support
• * NIST SP800-90 A/B/C Random Number Generator (RNG)
• * 16 MHz SPI interface to communicate security commands between the dsPIC core and the Secure Subsystem
• * Secure Subsystem’s authorization sessions can be used to prevent various kinds of attacks or denial of service
• * Secure Subsystem’s Advanced Crypto Engine algorithms have achieved JIL HIGH rating and are certified by FIPS as per Cryptographic Algorithm Validation Program (CAVP)
• * Secure Subsystem with FIPS 140-2 Level 2 with Physical Security Level 3 certification as per Cryptographic Module Validation Program (CMVP) [in progress]
• * CodeGuard security together with Flash OTP by ICSP Write Inhibit enables implementing Immutable Secure Boot
• * Flash configurable as One-Time Programmable (OTP) memory via ICSP Write Inhibit
• * Restricts ICSP programming/erasing operation on entire Flash memory when Flash OTP by Write Inhibit is activated using an external programmer/debugger
• * Does not allow execution from RAM
• * Support for disabling entry into debug mode
• * Support for secure provisioning
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• Secure Use Cases Support* Immutable secure boot – Code authentication
• * Secure bootloader
• * Secure communication
• * CAN message authentication
• * WPC 1.3 Qi high-power wireless charger authentication
• * Authentication and Session Establishment
• * X.509 Certificate Validation and Storage
• * IP Protection
• * Firmware attestation
• * Device authentication OCP-SPDM specification support
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• High-Speed PWM Module* 6 independent PWM pairs (12 total outputs) with up to 250ps resolution
• * Dead-time insertion for rising and falling edges and dead-time compensation support
• * Clock chopping for high-frequency operation
• * Fault and current limit inputs
• * Flexible trigger configuration for ADC triggering
• * Advanced Analog features
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• 5x 12-bit 3.5 MSPS ADC Modules each with 4 dedicated SARs and 1 shared SAR cores (5 S&Hs), 24 ADC input channels* 4 digital comparators and 4 oversampling filters up to 256x for increased resolution (up to 16-bits)
• * 6 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation
• * Up to 3 op amps with internal connection to ADC Module
• * 2 Current Bias Generators (CBGs)
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• [Functional Safety Support (ISO 26262 and IEC 61508)](https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/16-bit-mcus/functional-safety)* ASIL B automotive safety applications – ISO 26262
• * SIL 2 industrial safety applications – IEC 61508
• * ISO 26262 and IEC 61508 Functional Safety Packages
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• Timer/Counters/Output Compare/Input Capture* 21 16-bit timer/counters (up to 12 32-bit)
• * 12 PWM or Output Compare (OC) outputs
• * 9 Input Captures (IC) pins or internal connections from the CLC or Comparator Modules
• * 3 Quadrature Encoder Interface (QEI) Modules for optical encoder support
• * Peripheral Trigger Generator (PTG) for scheduling complex sequences
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• Communication Interfaces* 3 UARTs (15 Mbps) with automated protocol handling for LIN/J2602, DMX and IrDA®
• * 3x 4-wire SPI/I2S up to 40 MHz with dedicated pins
• * 3 I2C Modules (up to 1 Mbps) with SMBus support
• * 2 CAN Flexible Data Rate (CAN-FD) Module ("50x devices only)
• * 2 Single-Edge Nibble Transmission (SENT) Modules for sensor interfacing
• * 8 DMA channels supporting UART, SPI, ADC, CAN-FD, IC, OC and Timer data transfers
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• Special Features* 4 Configurable Logic Cell (CLC) Modules with user defined logic gate circuits
• * Programmable Pin Select (PPS) for peripheral pin function mapping
• * On-chip temperature sensor with direct ADC Module connection
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• Functional Safety Features* CodeGuard™ security for program FLASH
• * Programmable Cyclic Redundancy Check (CRC)
• * FLASH ECC Fault Injection testing feature
• * RAM Memory Built-In Self Test (MBIST)
• * Fail-Safe Clock Monitoring (FSCM) with redundant clock sources
• * Capless Internal Voltage Regulator
• * Virtual Pins for Redundancy and Monitoring
• * I/O Port read-back
• * Analog peripherals redundancies and more
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• [AUTOSAR-Ready DSC supporting](https://www.microchip.com/en-us/solutions/automotive-and-transportation/automotive-products/microcontrollers-and-microprocessors/dspic-dscs/autosar)* AUTOSAR (4.3.x) and ASIL B- and ASPICE-compliant MCAL drivers
• * ISO 26262 Functional Safety and Automotive Security
Description
AI
Microchip’s dsPIC33CK family of secure digital signal controllers (DSCs) with integrated Hardware Security Module (HSM) features a single 100 MHz dsPIC® DSC core with integrated DSP enhanced on-chip peripherals and secure subsystem.
Common Criteria Joint Interpretation Library (JIL) high-rated secure subsystem provides hardware-based cryptographic key storage and crypto accelerators for multiple asymmetric, symmetric, and hashing security protocols. The secure subsystem combined with CodeGuard Flash Security (immutable secure boot) and Flash OTP by ICSP™ Write Inhibit features supports an ultra-secure method for key agreement, sign-verify authentication for automotive in-vehicle networking, industrial and consumer applications. The security features in the dsPIC33C DSCs such as CodeGuard based Immutable Secure Boot, Flash OTP and others protect against remote digital attacks while the integrated secure subsystem provides extra security with physical anti-tampering and side channel attack protections to block access to embedded system credentials**.** The secure DSCs provide robust security measures for industrial and automotive environments, including code authentication (aka secure boot), message authentication via MAC generation, support for trusted firmware updates, Qi 1.3/2.0 wireless charging authentication, multiple key management protocols including TLS and other root-of-trust based operations to enable a high level of security for industrial and automotive systems. Additionally, these controllers enable developing secure power supplies with digital power capabilities satisfying the security requirement of the Open Compute Project (OCP) compliant power supply implementing SPDM protocol.
These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors. These DSCs are also ideal for switched mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC and other power circuits to reach the highest possible energy efficiency. These devices are also ideal for advanced sensing and control, touch, high-performance general-purpose and robust applications.
The dsPIC33CK product family has many hardware features that help simplify functional safety certifications for ASIL-B and SIL-2 focused automotive and industrial safety-critical applications. The family offers ISO 26262 and IEC 61508 Functional Safety packages containing FMEDA report, safety manual, diagnostic libraries and more. Learn more about [Functional Safety](https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/16-bit-mcus/functional-safety) capabilities including hardware, software, and supporting collateral
The documentation and additional resources related to the secure subsystem is available [under NDA](https://ww1.microchip.com/downloads/aemDocuments/documents/MCU16/ProductDocuments/Brochures/Accessing-dsPIC33-DSC-Related-Secure-Documents-00004802.pdf). Contact your local Microchip sales team for more information or our Client Success Team ([Schedule a Call](https://calendly.com/megan-loftus)) to get assistance with your design
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