PI7C9X3G606GP Series

6-port, 6-lane, PCIe 3.0 Packet Switch with GreenPacket Technology

Catalog

6-port, 6-lane, PCIe 3.0 Packet Switch with GreenPacket Technology

Part	Applications	Interface	Package / Case	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]
Diodes Inc PI7C9X3G606GPCFCAEX	6-Port/6-Lane Packet Switch	I2C JTAG PCI Express SPI	144-LFBGA	Surface Mount	0.99 V	0.9 V

Catalog

6-port, 6-lane, PCIe 3.0 Packet Switch with GreenPacket Technology

Key Features

• Port and Lane Configurations for 6-port/6-Lane PCI Express GEN3 packet switchConfigurable Upstream lane widths of x1 or x2Configurable Downstream port number up to 5Configurable Downstream lane widths of x1 or x2

• Configurable Upstream lane widths of x1 or x2

• Configurable Downstream port number up to 5

• Configurable Downstream lane widths of x1 or x2

• Reference Clock ManagementIntegrated PCIe Gen3 clock buffer for all downstream portsSupport three reference clock structures (Common, SRNS and SRIS)Handle SSC Isolation up to one portProvide two clock application modes (Base and CDSR)

• Integrated PCIe Gen3 clock buffer for all downstream ports

• Support three reference clock structures (Common, SRNS and SRIS)

• Handle SSC Isolation up to one port

• Provide two clock application modes (Base and CDSR)

• Power ManagementSupport 7 power states (P0/P0s/P1/P1.1/P1.2/P2/P1.2PG)Start-up power management scheme"Empty" Hot-Plug ports put in P2 stateSupport Message packet for System Power ManagementLatency Tolerance Reporting (LTR)Optimized Buffer Flush Fill (OBFF)

• Support 7 power states (P0/P0s/P1/P1.1/P1.2/P2/P1.2PG)

• Start-up power management scheme"Empty" Hot-Plug ports put in P2 state

• "Empty" Hot-Plug ports put in P2 state

• Support Message packet for System Power ManagementLatency Tolerance Reporting (LTR)Optimized Buffer Flush Fill (OBFF)

• Latency Tolerance Reporting (LTR)

• Optimized Buffer Flush Fill (OBFF)

• PHY and MAC LayersPHY initial settings optionally programmable through JTAG, EEPROM, and I2CAdaptive Continuous Time Linear Equalizer and 5-tap Decision Feedback Equalizer for RXAdaptive and programmable 3-tap TX equalizationRX Polarity Inversion and Lane Reversal

• PHY initial settings optionally programmable through JTAG, EEPROM, and I2C

• Adaptive Continuous Time Linear Equalizer and 5-tap Decision Feedback Equalizer for RX

• Adaptive and programmable 3-tap TX equalization

• RX Polarity Inversion and Lane Reversal

• Data Link LayerProgrammable ACK latency timer to respond ACK based upon traffic conditionConfigurable Flow Control Credit to balance bandwidth utilization and buffer usage

• Programmable ACK latency timer to respond ACK based upon traffic condition

• Configurable Flow Control Credit to balance bandwidth utilization and buffer usage

• Transaction LayerPacket forwarding options including Cut-Through and Store & ForwardSupport up to 512-Byte Max Payload SizeLow packet forwarding latency < 150ns (typical case)Access Control Service (ACS) for peer-to-peer trafficAddress Translation (AT) packet for SR-IOV applicationSupport Atomic operationSupport MulticastProvide Performance Visibility for ingress/egress packet types and packet counts

• Packet forwarding options including Cut-Through and Store & Forward

• Support up to 512-Byte Max Payload Size

• Low packet forwarding latency < 150ns (typical case)

• Access Control Service (ACS) for peer-to-peer traffic

• Address Translation (AT) packet for SR-IOV application

• Support Atomic operation

• Support Multicast

• Provide Performance Visibility for ingress/egress packet types and packet counts

• Dual-Host ApplicationSupport one Cross-Domain End-Point (CDEP) port for Host-to-Host CommunicationsSupport Fail-over using CDEP portProvide up to 4 physical or 8 virtual DMA channels enabling communications among Hosts and EPs

• Support one Cross-Domain End-Point (CDEP) port for Host-to-Host Communications

• Support Fail-over using CDEP port

• Provide up to 4 physical or 8 virtual DMA channels enabling communications among Hosts and EPs

• Reliability, Availability and ServiceabilityEnhanced Advanced Error ReportingEnd-to-End Data Protection with ECCError Handling MechanismSupport Surprise Hot RemovalSupport Downstream Port Containment (DPC)Support Hot Plug for Upstream and Downstream portProvide Serial Hot Plug TypeSupport LED ManagementThermal Sensor reporting operational temperature instantlyIEEE 1149.1 and 1149.6 JTAG interface support

• Enhanced Advanced Error Reporting

• End-to-End Data Protection with ECC

• Error Handling Mechanism

• Support Surprise Hot Removal

• Support Downstream Port Containment (DPC)

• Support Hot Plug for Upstream and Downstream port

• Provide Serial Hot Plug Type

• Support LED Management

• Thermal Sensor reporting operational temperature instantly

• IEEE 1149.1 and 1149.6 JTAG interface support

• Advanced Diagnostic Tools - PCIBUDDYTMPHY EyeTMMAC ViewerTM(including embedded LA and LTSSM monitor)PCIBUDDYTMOn-the-fly PRBS loopback testOn-the-fly Compliance pattern test

• PHY EyeTM

• MAC ViewerTM(including embedded LA and LTSSM monitor)

• PCIBUDDYTM

• On-the-fly PRBS loopback test

• On-the-fly Compliance pattern test

• Side-band Management InterfaceI2C/JTAGSPI EEPROM

• I2C/JTAG

• SPI EEPROM

• Standard ComplianceCompliant with PCI Express Base Specification Revision 3.1Compliant with PCI Express CEM Specification Revision 3.0Compliant with Advanced Configuration Power Interface (ACPI) Specification

• Compliant with PCI Express Base Specification Revision 3.1

• Compliant with PCI Express CEM Specification Revision 3.0

• Compliant with Advanced Configuration Power Interface (ACPI) Specification

• Power & PackageTypical power consumption: 2.5W (full-loading at Tj = 80℃)Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)Halogen and Antimony Free. "Green" Device (Note 3)For automotive applications requiring specific change control (i.e. parts qualified to AEC Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative.https://www.diodes.com/quality/product-definitions/Packages: 144-pin, FC-LFBGA, 10mm x 10mm package

• Typical power consumption: 2.5W (full-loading at Tj = 80℃)

• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)

• Halogen and Antimony Free. "Green" Device (Note 3)

• For automotive applications requiring specific change control (i.e. parts qualified to AEC Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative.https://www.diodes.com/quality/product-definitions/

• Packages: 144-pin, FC-LFBGA, 10mm x 10mm package

Description

The DIODES PI7C9X3G606GP is a PCIe GEN3 packet switch that supports 6 lanes of GEN3 SERDES in flexible 3- port, 5-port and 6-port configurations. The architecture of the PCIe packet switch allows the flexible port configuration by allocating variable lane widths for each port. The packet switch can be configured to have different port types such as upstream port, downstream ports and Cross-Domain End-Point (CDEP) ports to support various applications, which include port fan-out, dual-host connectivity. Inside the packet switch, multiple DMA channels are embedded to facilitate data communication more efficiently among host(s) and end-points.