SN74HC193-Q1 Series

High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counter with Asynchronous Reset

Catalog

High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counter with Asynchronous Reset

Part	Count Rate	Reset	Direction	Number of Bits per Element	Voltage - Supply [Min]	Voltage - Supply [Max]	Timing	Package / Case [x]	Package / Case	Package / Case [y]	Operating Temperature [Max]	Operating Temperature [Min]	Trigger Type	Number of Elements	Mounting Type	Logic Type	Supplier Device Package	Qualification	Grade	Package / Case	Package / Case
Texas Instruments SN74HC193PWR	24 MHz	Asynchronous	Down Up	4	2 V	6 V	Synchronous	0.173 in	16-TSSOP	4.4 mm	85 °C	-40 °C	Positive Edge	1	Surface Mount	Binary Counter	16-TSSOP
Texas Instruments SN74HC193DR	24 MHz	Asynchronous	Down Up	4	2 V	6 V	Synchronous	0.154 in	16-SOIC	3.9 mm	85 °C	-40 °C	Positive Edge	1	Surface Mount	Binary Counter	16-SOIC
Texas Instruments SN74HC193D	24 MHz	Asynchronous	Down Up	4	2 V	6 V	Synchronous	0.154 in	16-SOIC	3.9 mm	85 °C	-40 °C	Positive Edge	1	Surface Mount	Binary Counter	16-SOIC
Texas Instruments CD74HC193M	29 MHz	Asynchronous	Down Up	4	2 V	6 V	Synchronous	0.154 in	16-SOIC	3.9 mm	125 °C	-55 °C	Positive Edge	1	Surface Mount	Binary Counter	16-SOIC
Texas Instruments SN74HC193QPWRQ1	24 MHz	Asynchronous	Down Up	4	2 V	6 V	Synchronous	0.173 in	16-TSSOP	4.4 mm	85 °C	-40 °C	Positive Edge	1	Surface Mount	Binary Counter	16-TSSOP	AEC-Q100	Automotive
Texas Instruments SN74HC193DT	24 MHz	Asynchronous	Down Up	4	2 V	6 V	Synchronous	0.154 in	16-SOIC	3.9 mm	85 °C	-40 °C	Positive Edge	1	Surface Mount	Binary Counter	16-SOIC
Texas Instruments CD74HC193MT	29 MHz	Asynchronous	Down Up	4	2 V	6 V	Synchronous	0.154 in	16-SOIC	3.9 mm	125 °C	-55 °C	Positive Edge	1	Surface Mount	Binary Counter	16-SOIC
Texas Instruments SN74HC193QPWRG4Q1	24 MHz	Asynchronous	Down Up	4	2 V	6 V	Synchronous	0.173 in	16-TSSOP	4.4 mm	85 °C	-40 °C	Positive Edge	1	Surface Mount	Binary Counter	16-TSSOP	AEC-Q100	Automotive
Texas Instruments CD74HC193M96E4	29 MHz	Asynchronous	Down Up	4	2 V	6 V	Synchronous	0.154 in	16-SOIC	3.9 mm	125 °C	-55 °C	Positive Edge	1	Surface Mount	Binary Counter	16-SOIC
Texas Instruments CD74HC193E	29 MHz	Asynchronous	Down Up	4	2 V	6 V	Synchronous		16-DIP		125 °C	-55 °C	Positive Edge	1	Through Hole	Binary Counter	16-PDIP			0.3 in	7.62 mm

Catalog

High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counter with Asynchronous Reset

Key Features

• Synchronous Counting and Asynchronous LoadingTwo Outputs for N-Bit CascadingLook-Ahead Carry for High-Speed CountingFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHData sheet acquired from Harris SemiconductorSynchronous Counting and Asynchronous LoadingTwo Outputs for N-Bit CascadingLook-Ahead Carry for High-Speed CountingFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHData sheet acquired from Harris Semiconductor

Description

The ’HC193 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP or DOWN). The direction of counting is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD)\ input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs. A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and LOAD\ inputs. These counters were designed to be cascaded without the need for external circuitry. The borrow (BO)\ output produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO)\ output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counters then can be cascaded easily by feeding BO\ and CO\ to DOWN and UP, respectively, of the succeeding counter. The ’HC193 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP or DOWN). The direction of counting is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD)\ input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs. A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and LOAD\ inputs. These counters were designed to be cascaded without the need for external circuitry. The borrow (BO)\ output produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO)\ output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counters then can be cascaded easily by feeding BO\ and CO\ to DOWN and UP, respectively, of the succeeding counter.