Catalog
Next Generation HiFlex™ Ethernet Network Clock Generator
Key Features
• 3.3V & 2.5V supply voltage
• Crystal/CMOS input: 25 MHz
• Differential input: 25MHz, 125MHz, and 156.25 MHz
• Output frequencies: 312.5, 156.25, 125, 100, 50, 25MHz
• 4 Output banks with selectable output signaling: LVPECL or LVDS
• Low 0.3ps typical integrated phase noise design: 156.25MHz (12kHz to 20MHz)
• PLL Bypass mode for test
• Power supply noise rejection: -52 dBc typical @ VDD
• Packaging (Pb-free & Green): 56-lead 8×8mm TQFN
• Industrial temperature support: -40C to 85C
Description
AI
The PI6LC48S25B is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25MHz crystal input, while the PLL loop is used to generate the 156.25MHz and other Ethernet clock frequencies. An additional buffered crystal oscillator output is provided to serve as a low noise reference for other circuitry.