SN74AUC1G126 Series

Single 0.8-V to 2.7-V high speed buffer with 3-state outputs

Catalog

Single 0.8-V to 2.7-V high speed buffer with 3-state outputs

Part	Number of Elements	Logic Type	Supplier Device Package [x]	Supplier Device Package	Supplier Device Package [y]	Number of Bits per Element	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Mounting Type	Output Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]
Texas Instruments SN74AUC1G126YZTR	1	Buffer Non-Inverting	1.4	5-DSBGA	0.9	1	85 °C	-40 °C	5-XFBGA DSBGA	Surface Mount	3-State	2.7 V	0.8 V	9 mA	9 mA
Texas Instruments SN74AUC1G126YEPR	1	Buffer Non-Inverting	1.4	5-DSBGA	0.9	1	85 °C	-40 °C	5-XFBGA DSBGA	Surface Mount	3-State	2.7 V	0.8 V	9 mA	9 mA
Texas Instruments 74AUC1G126DCKRG4	1	Buffer Non-Inverting		SC-70-5		1	85 °C	-40 °C	5-TSSOP SC-70-5 SOT-353	Surface Mount	3-State	2.7 V	0.8 V	9 mA	9 mA
Texas Instruments SN74AUC1G126YZPR	1	Buffer Non-Inverting	1.4	5-DSBGA	0.9	1	85 °C	-40 °C	5-XFBGA DSBGA	Surface Mount	3-State	2.7 V	0.8 V	9 mA	9 mA
Texas Instruments SN74AUC1G126DBVR	1	Buffer Non-Inverting		SOT-23-5		1	85 °C	-40 °C	SC-74A SOT-753	Surface Mount	3-State	2.7 V	0.8 V	9 mA	9 mA
Texas Instruments SN74AUC1G126DCKR	1	Buffer Non-Inverting		SC-70-5		1	85 °C	-40 °C	5-TSSOP SC-70-5 SOT-353	Surface Mount	3-State	2.7 V	0.8 V	9 mA	9 mA

Catalog

Single 0.8-V to 2.7-V high speed buffer with 3-state outputs

Key Features

• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Available in TI’s NanoFree™ PackageOptimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial Power Down Mode and Back Drive ProtectionSub-1 V OperableMaximum tpdof 2.5 ns at 1.8 VLow Power Consumption, 10-µA Maximum ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Available in TI’s NanoFree™ PackageOptimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial Power Down Mode and Back Drive ProtectionSub-1 V OperableMaximum tpdof 2.5 ns at 1.8 VLow Power Consumption, 10-µA Maximum ICC±8-mA Output Drive at 1.8 V

Description

The SN74AUC1G126 bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. The SN74AUC1G126 device is a single line driver with a tri-state output. The output is disabled when the output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. NanoFree™ package technology is a major breakthrough in device packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, which prevents damaging current backflow through the device when it is powered down. The SN74AUC1G126 bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. The SN74AUC1G126 device is a single line driver with a tri-state output. The output is disabled when the output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. NanoFree™ package technology is a major breakthrough in device packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, which prevents damaging current backflow through the device when it is powered down.