SY898533L Series

Catalog

3.3V LVPECL 1:4 FANOUT BUFFER 20 TSSOP 4.4MM TUBE ROHS COMPLIANT: YES

Part	Type	Output	Supplier Device Package	Mounting Type	Input	Ratio - Input:Output [custom]	Frequency - Max [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case [y]	Package / Case	Package / Case [x]	Number of Circuits	Voltage - Supply [Max]	Voltage - Supply [Min]
Microchip Technology SY898533LKZ
Microchip Technology SY898533LKZ	Fanout Buffer (Distribution), Multiplexer	LVPECL	20-TSSOP	Surface Mount	CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL	2:4	650 MHz	70 °C	0 °C	4.4 mm	20-TSSOP	0.173 in	1	3.465 V	3.135 V
Microchip Technology SY898533LKZ-TR	Fanout Buffer (Distribution), Multiplexer	LVPECL	20-TSSOP	Surface Mount	CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL	2:4	650 MHz	70 °C	0 °C	4.4 mm	20-TSSOP	0.173 in	1	3.465 V	3.135 V

Key Features

• * Provides four differential 3.3V LVPECL copies

• * Selects between differential CLK, /CLK or LVPECL clock inputs

• * CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL input levels

• * PCLK, /PCLK pair accepts LVPECL, CML, SSTL input levels

• * 650MHz Maximum output frequency

• * <1.4ns Propagation delay (In-to-Q)

• * <30ps Output skew

• * <150ps Part-to-part skew

• * 3.3V ±5% supply voltage

• * 0°C to +70°C temperature operating range

• * Available in a 20-pin TSSOP package

Description

The SY898533L is a 3.3V, low skew, 1:4 LVPECL fanout buffer with two selectable clock input pairs. Most standard differential input levels can be applied to the CLK, /CLK pair while LVPECL, CML, or SSTL input levels can be applied to the PCLK, /PCLK pair. To eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin, the clock enable is synchronized with the input signal.The SY898533L operates from a 3.3V ±5% supply and is guaranteed over the full industrial temperature range of 0°C to +70°C. The SY898533L is part of Micrel's highspeed, Precision Edge® product line.