100EPT26 Series

Translator, 1:2 Fanout Differential LVPECL / LVDS to LVTTL

Catalog

Translator, 1:2 Fanout Differential LVPECL / LVDS to LVTTL

Part	Channel Type	Input Signal	Number of Circuits	Translator Type	Supplier Device Package	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Package / Case	Package / Case [custom]	Package / Case	Channels per Circuit	Output Signal	Package / Case [y]	Package / Case [x]
ON Semiconductor MC100EPT26DTR2	Unidirectional	LVDS, LVPECL	1	Mixed Signal	8-TSSOP	Non-Inverted	85 °C	-40 °C	Surface Mount	8-MSOP, 8-TSSOP	0.118 in	3 mm	2	LVTTL
ON Semiconductor MC100EPT26D	Unidirectional		1	Mixed Signal	8-SOIC	Non-Inverted	85 °C	-40 °C	Surface Mount	8-SOIC			2	LVTTL	3.9 mm	0.154 in
ON Semiconductor MC100EPT26DTR2G	Unidirectional	LVDS, LVPECL	1	Mixed Signal	8-TSSOP	Non-Inverted	85 °C	-40 °C	Surface Mount	8-MSOP, 8-TSSOP	0.118 in	3 mm	2	LVTTL
ON Semiconductor MC100EPT26MNR4G	Unidirectional	LVDS, LVPECL	1	Mixed Signal	8-DFN (2x2)	Non-Inverted	85 °C	-40 °C	Surface Mount	8-VFDFN Exposed Pad			2	LVTTL
ON Semiconductor MC100EPT26DTG	Unidirectional	LVDS, LVPECL	1	Mixed Signal	8-TSSOP	Non-Inverted	85 °C	-40 °C	Surface Mount	8-MSOP, 8-TSSOP	0.118 in	3 mm	2	LVTTL
ON Semiconductor MC100EPT26MNR4	Unidirectional	LVDS, LVPECL	1	Mixed Signal	8-DFN (2x2)	Non-Inverted	85 °C	-40 °C	Surface Mount	8-VFDFN Exposed Pad			2	LVTTL

Catalog

Translator, 1:2 Fanout Differential LVPECL / LVDS to LVTTL

Key Features

• 1.4ns Typical Propagation Delay

• Maximum Frequency > 275 MHz Typical

• The 100 Series Contains Temperature Compensation

• Operating Range: VCC= 3.0 V to 3.6 V with GND = 0 V

• Open Input Default State

• Safety Clamp on Inputs

• 24mA TTL outputs

• Q Outputs will default LOW with inputs open or at VEE

• VBBOutput

• Pb-Free Packages are Available

Description

The MC100EPT26 is a 1:2 Fanout Differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the 1:2 fanout design of the EPT26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board.The VBBoutput allows the EPT26 to be used in a single-ended input mode. In this mode the VBBoutput is tied to the D0bar input for a non-inverting buffer or the D0 input for an inverting buffer. If used, the VBBpin should be bypassed to ground via a 0.01 uF capacitator.