SN74ACT7803 Series

512 x 18 synchronous FIFO memory

Catalog

512 x 18 synchronous FIFO memory

Part	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Expansion Type	Data Rate	Bus Directional	Access Time	Operating Temperature [Max]	Package / Case	Package / Case	Package / Case	Supplier Device Package	Function	Current - Supply (Max) [Max]
Texas Instruments SN74ACT7803-40DL	4.5 V	5.5 V	Surface Mount	Width	25 MHz	Uni-Directional	20 ns	70 °C	0.295 in	56-BSSOP	7.5 mm	56-SSOP	Synchronous	400 µA
Texas Instruments SN74ACT7803-15DLR	4.5 V	5.5 V	Surface Mount	Width	67 MHz	Uni-Directional	12 ns	70 °C	0.295 in	56-BSSOP	7.5 mm	56-SSOP	Synchronous	400 µA
Texas Instruments SN74ACT7803-20DLR	4.5 V	5.5 V	Surface Mount	Width	50 MHz	Uni-Directional	13 ns	70 °C	0.295 in	56-BSSOP	7.5 mm	56-SSOP	Synchronous	400 µA
Texas Instruments SN74ACT7803-40DLR	4.5 V	5.5 V	Surface Mount	Width	25 MHz	Uni-Directional	20 ns	70 °C	0.295 in	56-BSSOP	7.5 mm	56-SSOP	Synchronous	400 µA
Texas Instruments SN74ACT7803-15DL	4.5 V	5.5 V	Surface Mount	Width	67 MHz	Uni-Directional	12 ns	70 °C	0.295 in	56-BSSOP	7.5 mm	56-SSOP	Synchronous	400 µA
Texas Instruments SN74ACT7803-25DL	4.5 V	5.5 V	Surface Mount	Width	40 MHz	Uni-Directional	15 ns	70 °C	0.295 in	56-BSSOP	7.5 mm	56-SSOP	Synchronous	400 µA
Texas Instruments SN74ACT7803-25DLR	4.5 V	5.5 V	Surface Mount	Width	40 MHz	Uni-Directional	15 ns	70 °C	0.295 in	56-BSSOP	7.5 mm	56-SSOP	Synchronous	400 µA

Catalog

512 x 18 synchronous FIFO memory

Key Features

• Member of the Texas Instruments WidebusTMFamilyFree-Running Read and Write Clocks Can Be Asynchronous or CoincidentRead and Write Operations Synchronized to Independent System ClocksInput-Ready Flag Synchronized to Write ClockOutput-Ready Flag Synchronized to Read Clock512 Words by 18 BitsLow-Power Advanced CMOS TechnologyHalf-Full Flag and Programmable Almost-Full/Almost-Empty FlagBidirectional Configuration and Width Expansion Without Additional LogicFast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching SimultaneouslyData Rates up to 67 MHzPin-to-Pin Compatible With SN74ACT7805 and SN74ACT7813Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center SpacingWidebus and OEC are trademarks of Texas Instruments Incorporated.Member of the Texas Instruments WidebusTMFamilyFree-Running Read and Write Clocks Can Be Asynchronous or CoincidentRead and Write Operations Synchronized to Independent System ClocksInput-Ready Flag Synchronized to Write ClockOutput-Ready Flag Synchronized to Read Clock512 Words by 18 BitsLow-Power Advanced CMOS TechnologyHalf-Full Flag and Programmable Almost-Full/Almost-Empty FlagBidirectional Configuration and Width Expansion Without Additional LogicFast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching SimultaneouslyData Rates up to 67 MHzPin-to-Pin Compatible With SN74ACT7805 and SN74ACT7813Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center SpacingWidebus and OEC are trademarks of Texas Instruments Incorporated.

Description

The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCCand GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7803 is characterized for operation from 0°C to 70°C. The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCCand GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7803 is characterized for operation from 0°C to 70°C.