SN74ALVCH162721 Series

3.3-V 20-Bit Flip-Flop With 3-State Outputs

Catalog

3.3-V 20-Bit Flip-Flop With 3-State Outputs

Part	Operating Temperature [Max]	Operating Temperature [Min]	Function	Package / Case	Package / Case	Package / Case	Number of Bits per Element	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Clock Frequency	Trigger Type	Number of Elements	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Output Type	Type	Input Capacitance
Texas Instruments SN74ALVCH162721DL	85 °C	-40 °C	Standard	0.295 in	56-BSSOP	7.5 mm	20	12 mA	12 mA	150 MHz	Positive Edge	1	56-SSOP	1.65 V	3.6 V	Surface Mount	Non-Inverted Tri-State	D-Type	3.5 pF
Texas Instruments SN74ALVCH162721DLR	85 °C	-40 °C	Standard	0.295 in	56-BSSOP	7.5 mm	20	12 mA	12 mA	150 MHz	Positive Edge	1	56-SSOP	1.65 V	3.6 V	Surface Mount	Non-Inverted Tri-State	D-Type	3.5 pF
Texas Instruments SN74ALVCH162721GR	85 °C	-40 °C	Standard	0.24 in	56-TFSOP	6.1 mm	20	12 mA	12 mA	150 MHz	Positive Edge	1	56-TSSOP	1.65 V	3.6 V	Surface Mount	Non-Inverted Tri-State	D-Type	3.5 pF

Catalog

3.3-V 20-Bit Flip-Flop With 3-State Outputs

Key Features

• Member of the Texas Instruments Widebus™ FamilyEPIC™ (Enhanced-Performance Implanted CMOS) Submicron ProcessOutput Ports Have Equivalent 26-Series Resistors, So No External Resistors Are RequiredESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA Per JESD 17Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsPackage Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) PackagesNOTE: For tape and reel order entry: The DGGR package is abbreviated to GR.Widebus, EPIC are trademarks of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyEPIC™ (Enhanced-Performance Implanted CMOS) Submicron ProcessOutput Ports Have Equivalent 26-Series Resistors, So No External Resistors Are RequiredESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA Per JESD 17Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsPackage Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) PackagesNOTE: For tape and reel order entry: The DGGR package is abbreviated to GR.Widebus, EPIC are trademarks of Texas Instruments.

Description

This 20-bit flip-flop is designed for low-voltage 1.65-V to 3.6-V VCCoperation. The 20 flip-flops of the SN74ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored. A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The outputs, which are designed to sink up to 12 mA, include equivalent 26-resistors to reduce overshoot and undershoot. The SN74ALVCH162721 is characterized for operation from –40°C to 85°C. This 20-bit flip-flop is designed for low-voltage 1.65-V to 3.6-V VCCoperation. The 20 flip-flops of the SN74ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored. A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The outputs, which are designed to sink up to 12 mA, include equivalent 26-resistors to reduce overshoot and undershoot. The SN74ALVCH162721 is characterized for operation from –40°C to 85°C.