SN74ALS175 Series

Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear

Catalog

Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear

Part	Package / Case	Package / Case [x]	Package / Case [y]	Operating Temperature [Max]	Operating Temperature [Min]	Trigger Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Number of Bits per Element	Clock Frequency	Number of Elements	Supplier Device Package	Type	Output Type	Max Propagation Delay @ V, Max CL	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Quiescent (Iq)	Package / Case	Package / Case
Texas Instruments SN74ALS175DR	16-SOIC	0.154 in	3.9 mm	70 °C	0 °C	Positive Edge	4.5 V	5.5 V	4	50 MHz	1	16-SOIC	D-Type	Complementary	17 ns	Surface Mount	400 µA	8 mA	14 mA
Texas Instruments SN74ALS175D	16-SOIC	0.154 in	3.9 mm	70 °C	0 °C	Positive Edge	4.5 V	5.5 V	4	50 MHz	1	16-SOIC	D-Type	Complementary	17 ns	Surface Mount	400 µA	8 mA	14 mA
Texas Instruments SN74ALS175NSR	16-SOIC			70 °C	0 °C	Positive Edge	4.5 V	5.5 V	4	50 MHz	1	16-SO	D-Type	Complementary	17 ns	Surface Mount	400 µA	8 mA	14 mA	0.209 "	5.3 mm
Texas Instruments SN74ALS175N	16-DIP			70 °C	0 °C	Positive Edge	4.5 V	5.5 V	4	50 MHz	1	16-PDIP	D-Type	Complementary	17 ns	Through Hole	400 µA	8 mA	14 mA	0.3 in	7.62 mm
Texas Instruments SN74ALS175NSLE

Catalog

Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear

Key Features

• ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct-Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsFully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct-Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsFully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

Description

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits. These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits.