100EL32 Series

Catalog

MULTIPLIER/DIVIDER, DIVIDE BY 2, 1 INPUT, 3 GHZ, 3.3 V TO 5 V, 8 PINS, SOIC

Part	Supplier Device Package	Logic Type	Count Rate	Trigger Type	Number of Elements	Number of Bits per Element	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case	Package / Case [y]	Package / Case [x]	Reset
Microchip Technology SY100EL32VZG	8-SOIC	Divide-by-2	3 GHz	Negative, Positive	1	1	85 °C	-40 °C	Surface Mount	3.3 V	5 V	8-SOIC	3.9 mm	0.154 in	Asynchronous
Microchip Technology SY100EL32VZI-TR	8-SOIC	Divide-by-2	3 GHz	Negative, Positive	1	1	85 °C	-40 °C	Surface Mount	3.3 V	5 V	8-SOIC	3.9 mm	0.154 in	Asynchronous
Microchip Technology SY100EL32VZG
Microchip Technology SY100EL32VZC	8-SOIC	Divide-by-2	3 GHz	Negative, Positive	1	1	85 °C	-40 °C	Surface Mount	3.3 V	5 V	8-SOIC	3.9 mm	0.154 in	Asynchronous
Microchip Technology SY100EL32VZI	8-SOIC	Divide-by-2	3 GHz	Negative, Positive	1	1	85 °C	-40 °C	Surface Mount	3.3 V	5 V	8-SOIC	3.9 mm	0.154 in	Asynchronous

Catalog

Key Features

• * 3.3V and 5V power supply options510ps propagation delay3.0GHz toggle frequencyHigh bandwidth output transistionsInternal 75KO input pull-down resistorsAvailable in 8-pin SOIC package

•

• + 3.3V and 5V power supply options510ps propagation delay3.0GHz toggle frequencyHigh bandwidth output transistionsInternal 75KO input pull-down resistorsAvailable in 8-pin SOIC package

•

• + 3.3V and 5V power supply options

• + 510ps propagation delay

• + 3.0GHz toggle frequency

• + High bandwidth output transistions

• + Internal 75KO input pull-down resistors

• + Available in 8-pin SOIC package

Description

The SY100EL32V is an integrated divide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The Reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state. The Reset allows for the synchronization of multiple EL32Vs in a system.