ADSP-BF561 Series
Blackfin Symmetric Multi-Processor for Consumer Multimedia
Manufacturer: Analog Devices Inc
Catalog
Blackfin Symmetric Multi-Processor for Consumer Multimedia
| Part | Interface | Clock Rate | Voltage - Core | On-Chip RAM | Voltage - I/O | Operating Temperature [Max] | Operating Temperature [Min] | Type | Package / Case | Non-Volatile Memory | Supplier Device Package | Mounting Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Analog Devices Inc ADSP-BF561SBBCZ-5A | SPI, SSP, UART | 533 MHz | 1.25 V | 328 kB | 2.5 V, 3.3 V | 85 °C | -40 °C | Fixed Point | 256-BGA, CSPBGA | External | 256-CSPBGA (17x17) | Surface Mount |
Key Features
• Dual Blackfin cores with each core capable of 600 MHz/1200 MMACs (2400 MMACs total) for demanding signal processing applications.
• Large On-Chip Memory of 328 KBytes – arranged as individual L1 memory systems for each core plus a shared L2 memory space.
• High data throughput tailored for the needs of imaging and consumer multimedia applications.
• Application Tuned Peripherals provide glueless connectivity to a variety of audio/video converters and general-purpose ADCs/DACs.
Description
AI
The Blackfin®Processor family expands the performance envelope with the ADSP-BF561. With two high performance Blackfin Processor cores, flexible cache architecture, enhanced DMA subsystem, and Dynamic Power Management (DPM) functionality, the ADSP-BF561 can support complex control and signal processing tasks while maintaining extremely high data throughput.The ADSP-BF561 is a functional extension of the popular Blackfin Processor family and is ideally suited for a broad range of industrial, instrumentation, medical, and consumer appliance applications—allowing for scalability based upon the required data bandwidth and mix of control, plus signal processing needed in the end product.High-Level of Integration328 KBytes of on-chip memory configured as:32 KBytes of L1 instruction memory SRAM/Cache per core64 KBytes of L1 data memory SRAM/Cache per core4 KBytes of L1 scratchpad memory per core128 KBytes of low-latency shared L2 memory32-bit Memory Controller providing glueless connection to multiple banks of SDRAM, SRAM, Flash or ROM.Two Parallel Peripheral Interfaces Units supporting ITU-R 656 video data formats.Two dual-channel, full-duplex, synchronous serial ports supporting eight stereo I2S channels.Dual 16 Channel DMA Controllers, supporting one and two-dimension transfers.SPI-compatible Port.UART with support for IrDA®.12 timer/counters supporting PWM, pulsewidth and event count modes.48 Programmable Flags/General Purpose I/O.Event Handler.Dual Watchdog timers.PLL capable of 1x to 63x frequency multiplication.256-ball Mini-BGA and 297-ball Sparse PBGA packages.