SN74ABT162827A Series

20-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Catalog

20-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Part	Output Type	Package / Case	Package / Case	Package / Case	Number of Bits per Element	Number of Elements	Mounting Type	Logic Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]
Texas Instruments SN74ABT162827DL
Texas Instruments SN74ABT162827DGGR
Texas Instruments SN74ABT162827ADLR	3-State	0.295 in	56-BSSOP	7.5 mm	10	2	Surface Mount	Buffer Non-Inverting	12 mA	12 mA	85 °C	-40 °C	56-SSOP	4.5 V	5.5 V

Catalog

20-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Key Features

• Members of the Texas Instruments Widebus™ FamilyOutput Ports Have Equivalent 25-Series Resistors, So No External Resistors Are RequiredHigh-Impedance State During Power Up and Power DownTypical VOLP(Output Ground Bounce)< 1 V at VCC= 5 V, TA= 25°CDistributed VCCand GND Pin Minimizes High-Speed Switching NoiseIoffand Power-Up 3-State Support Hot InsertionFlow-Through Architecture Optimizes PCB LayoutLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Widebus is a trademark of Texas Instruments.Members of the Texas Instruments Widebus™ FamilyOutput Ports Have Equivalent 25-Series Resistors, So No External Resistors Are RequiredHigh-Impedance State During Power Up and Power DownTypical VOLP(Output Ground Bounce)< 1 V at VCC= 5 V, TA= 25°CDistributed VCCand GND Pin Minimizes High-Speed Switching NoiseIoffand Power-Up 3-State Support Hot InsertionFlow-Through Architecture Optimizes PCB LayoutLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Widebus is a trademark of Texas Instruments.

Description

The ’ABT162827A devices are noninverting 20-bit buffers composed of two 10-bit buffers with separate output-enable signals. For either 10-bit buffer, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-series resistors to reduce overshoot and undershoot. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The ’ABT162827A devices are noninverting 20-bit buffers composed of two 10-bit buffers with separate output-enable signals. For either 10-bit buffer, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-series resistors to reduce overshoot and undershoot. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.