Catalog
Ultra low-power 32 Mbit Serial SPI Page EEPROM
Key Features
• Interface
- Supports serial peripheral interface (SPI) and dual/quad outputs
• High speed frequency
- Clock frequency up to 80MHz
- Fast read single/dual/quad output with one dummy byteDual output data transfer up to 160Mbits/sQuad output data transfer up to 320Mbits/s
• Memory
- 32 Mbits of page EEPROM
- 64-Kbyte blocks, 4-Kbyte sectors
- Page size: 512-byte
- Two additional 512-byte identification pages
• Temperature
- Operating temperature range:-40 °C to +85 °C (industrial)-40 °C to +105 °C (extended)
• Performance
- Write endurance: 500 kcycles on full temperature range
- Data retention:100 years10 years after 500 kcycles
Description
AI
The M95P32-I and M95P32-E are manufactured with ST's advanced proprietary NVM technology. They offer byte flexibility, page alterability, high page cycling performance, and ultra-low power consumption, equivalent to that of EEPROM technology.
The M95P32-I and M95P32-E are a 32-Mbit SPI page EEPROM device organized as 8192 programmable pages of 512 bytes each, accessed through an SPI bus with high-performance dual- and quad-SPI outputs.
The devices offer two additional (identification) 512-byte pages:
Additional status, configuration and volatile registers set the desired device configuration, while the safety register provides information on the device status.
The M95P32-I operates with a supply voltage from 1.6 to 3.6 V over an ambient temperature range of -40 °C to +85 °C. The M95P32-E offers an extended range of temperature of -40°C to +105 °C. The device supports a clock frequency of up to 80 MHz.
The M95P32-I and M95P32-E offer byte and page write instructions of up to 512 bytes. Write instructions consist in self-timed auto erase and program operations, resulting in flexible data byte management.
The devices also accept page/block/sector/chip erase commands to set the memory to an erased state.
The memory can then be fast-programmed by 512-byte pages, and further optimized using the Page program with buffer load instruction to hide the SPI communication latency.